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authorMartin Hunt <hunt@redhat.com>1996-08-29 00:35:11 +0000
committerMartin Hunt <hunt@redhat.com>1996-08-29 00:35:11 +0000
commitd70b4d426ba96845c0a40138c5d3ee05ac279ca5 (patch)
tree3608600955a1dde8fc42f76e745e760847636a4c /sim/d10v/interp.c
parente7dd77751d79943b39a1d2308678d28309a000e1 (diff)
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Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
Diffstat (limited to 'sim/d10v/interp.c')
-rw-r--r--sim/d10v/interp.c226
1 files changed, 171 insertions, 55 deletions
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index 279a6cb..20cbdbe 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -1,3 +1,4 @@
+#include <signal.h>
#include "sysdep.h"
#include "bfd.h"
#include "remote-sim.h"
@@ -59,30 +60,56 @@ lookup_hash (ins, size)
}
uint32
-get_longword_swap (x)
- uint16 x;
+get_longword (x)
+ uint8 *x;
{
- uint8 *a = (uint8 *)(x + State.imem);
+ uint8 *a = x;
return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]);
}
+int64
+get_longlong (x)
+ uint8 *x;
+{
+ uint8 *a = x;
+ return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) +
+ ((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7];
+}
+
uint16
-get_word_swap (x)
- uint16 x;
+get_word (x)
+ uint8 *x;
{
- uint8 *a = (uint8 *)(x + State.imem);
- return (a[0]<<8) + a[1];
+ uint8 *a = x;
+ return ((uint16)a[0]<<8) + a[1];
}
void
-write_word_swap (addr, data)
- uint16 addr, data;
+write_word (addr, data)
+ uint8 *addr;
+ uint16 data;
{
- uint8 *a = (uint8 *)(addr + State.imem);
+ uint8 *a = addr;
a[0] = data >> 8;
a[1] = data & 0xff;
}
+void
+write_longlong (addr, data)
+ uint8 *addr;
+ int64 data;
+{
+ uint8 *a = addr;
+ a[0] = data >> 56;
+ a[1] = (data >> 48) & 0xff;
+ a[2] = (data >> 40) & 0xff;
+ a[3] = (data >> 32) & 0xff;
+ a[4] = (data >> 24) & 0xff;
+ a[5] = (data >> 16) & 0xff;
+ a[6] = (data >> 8) & 0xff;
+ a[7] = data & 0xff;
+}
+
static void
get_operands (struct simops *s, uint32 ins)
@@ -127,26 +154,35 @@ do_parallel (ins1, ins2)
uint16 ins1, ins2;
{
struct hash_entry *h1, *h2;
- /* printf ("do_parallel %x || %x\n",ins1,ins2); */
+ /* printf ("do_parallel %x || %x\n",ins1,ins2); */
h1 = lookup_hash (ins1, 0);
- get_operands (h1->ops, ins1);
h2 = lookup_hash (ins2, 0);
- get_operands (h2->ops, ins2);
+
if (h1->ops->exec_type == PARONLY)
{
+ get_operands (h1->ops, ins1);
(h1->ops->func)();
if (State.exe)
- (h2->ops->func)();
+ {
+ get_operands (h2->ops, ins2);
+ (h2->ops->func)();
+ }
}
else if (h2->ops->exec_type == PARONLY)
{
+ get_operands (h2->ops, ins2);
(h2->ops->func)();
if (State.exe)
- (h1->ops->func)();
+ {
+ get_operands (h1->ops, ins1);
+ (h1->ops->func)();
+ }
}
else
{
+ get_operands (h1->ops, ins1);
(h1->ops->func)();
+ get_operands (h2->ops, ins2);
(h2->ops->func)();
}
}
@@ -190,7 +226,7 @@ sim_write (addr, buffer, size)
int i;
init_system ();
- printf ("sim_write %d bytes to 0x%x\n",size,addr);
+ /* printf ("sim_write %d bytes to 0x%x\n",size,addr); */
for (i = 0; i < size; i++)
{
State.imem[i+addr] = buffer[i];
@@ -257,44 +293,50 @@ sim_resume (step, siggnal)
int i;
reg_t oldpc;
- printf ("sim_resume %d %d\n",step,siggnal);
+/* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
- while (1)
- {
- inst = RLW (PC << 2);
- oldpc = PC;
- switch (inst & 0xC0000000)
- {
- case 0xC0000000:
- /* long instruction */
- do_long (inst & 0x3FFFFFFF);
- break;
- case 0x80000000:
- /* R -> L */
- do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
- break;
- case 0x40000000:
- /* L -> R */
- do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
- break;
- case 0:
- do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
- break;
- }
-
- if (State.RP && PC == RPT_E)
- {
- RPT_C -= 1;
- if (RPT_C == 0)
- State.RP = 0;
- else
- PC = RPT_S;
- }
-
- /* FIXME */
- if (PC == oldpc)
- PC++;
- }
+ if (step)
+ State.exception = SIGTRAP;
+ else
+ State.exception = 0;
+
+ do
+ {
+ inst = RLW (PC << 2);
+ oldpc = PC;
+ switch (inst & 0xC0000000)
+ {
+ case 0xC0000000:
+ /* long instruction */
+ do_long (inst & 0x3FFFFFFF);
+ break;
+ case 0x80000000:
+ /* R -> L */
+ do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
+ break;
+ case 0x40000000:
+ /* L -> R */
+ do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
+ break;
+ case 0:
+ do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
+ break;
+ }
+
+ if (State.RP && PC == RPT_E)
+ {
+ RPT_C -= 1;
+ if (RPT_C == 0)
+ State.RP = 0;
+ else
+ PC = RPT_S;
+ }
+
+ /* FIXME */
+ if (PC == oldpc)
+ PC++;
+ }
+ while (!State.exception);
}
int
@@ -308,7 +350,7 @@ void
sim_info (verbose)
int verbose;
{
- printf ("sim_verbose\n");
+ printf ("sim_info\n");
}
void
@@ -341,5 +383,79 @@ sim_stop_reason (reason, sigrc)
enum sim_stop *reason;
int *sigrc;
{
- printf ("sim_stop_reason\n");
+/* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */
+
+ if (State.exception == SIGQUIT)
+ {
+ *reason = sim_exited;
+ *sigrc = State.exception;
+ }
+ else
+ {
+ *reason = sim_stopped;
+ *sigrc = State.exception;
+ }
+}
+
+void
+sim_fetch_register (rn, memory)
+ int rn;
+ unsigned char *memory;
+{
+ if (rn > 31)
+ {
+ WRITE_64 (memory, State.a[rn-32]);
+ /* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
+ }
+ else
+ {
+ WRITE_16 (memory, State.regs[rn]);
+ /* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
+ }
+}
+
+void
+sim_store_register (rn, memory)
+ int rn;
+ unsigned char *memory;
+{
+ if (rn > 31)
+ {
+ State.a[rn-32] = READ_64 (memory) & MASK40;
+ /* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
+ }
+ else
+ {
+ State.regs[rn]= READ_16 (memory);
+ /* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */
+ }
}
+
+sim_read (addr, buffer, size)
+ SIM_ADDR addr;
+ unsigned char *buffer;
+ int size;
+{
+ int i;
+ for (i = 0; i < size; i++)
+ {
+ buffer[i] = State.imem[addr + i];
+ }
+ return size;
+}
+
+void
+sim_do_command (cmd)
+ char *cmd;
+{
+ printf("sim_do_command: %s\n",cmd);
+}
+
+int
+sim_load (prog, from_tty)
+ char *prog;
+ int from_tty;
+{
+ /* Return nonzero so GDB will handle it. */
+ return 1;
+}