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| author | Fred Fish <fnf@specifix.com> | 1997-12-02 23:13:56 +0000 |
|---|---|---|
| committer | Fred Fish <fnf@specifix.com> | 1997-12-02 23:13:56 +0000 |
| commit | 193e528cd4da8e54b2d8b1a34c86da5c9a0599da (patch) | |
| tree | 57825bff58d38fa109f3a80ef033f52a9b066935 /sim/d10v/ChangeLog | |
| parent | 28ad0632ee28db8d1ca68075e0254ab20f1f9c81 (diff) | |
| download | gdb-193e528cd4da8e54b2d8b1a34c86da5c9a0599da.zip gdb-193e528cd4da8e54b2d8b1a34c86da5c9a0599da.tar.gz gdb-193e528cd4da8e54b2d8b1a34c86da5c9a0599da.tar.bz2 | |
* interp.c (sim_resume): Call do_2_short with LEFT_FIRST or
RIGHT_FIRST, as appropriate, instead of hardcoded ints that
don't match enum values.
PR 13496
Diffstat (limited to 'sim/d10v/ChangeLog')
| -rw-r--r-- | sim/d10v/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 013b93d..8612dbd 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,9 +1,16 @@ +Tue Dec 2 15:38:34 1997 Fred Fish <fnf@cygnus.com> + + * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or + RIGHT_FIRST, as appropriate, instead of hardcoded ints that + don't match enum values. + Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com> * simops.c (OP_3A00): For "macu", perform multiply stage using 32 bit rather than 16 bit precision. (OP_3C00): For "mulxu", store unsigned product in ACC. (OP_3800): For "msbu", subtract unsigned product from ACC, + (OP_0): For "sub", compute carry by comparing inputs. Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com> |