* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.

	(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
	(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
	instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.

7 files changed, 229 insertions, 222 deletions

diff --git a/sim/cris/cpuall.h b/sim/cris/cpuall.h
index fabbdb2..237594a 100644
--- a/sim/cris/cpuall.h
+++ b/sim/cris/cpuall.h
@@ -29,35 +29,30 @@ This file is part of the GNU simulators.
 
 #ifdef WANT_CPU_CRISV0F
 #include "engv0.h"
-#include "cgen-engine.h"
 #include "cpuv0.h"
 #include "decodev0.h"
 #endif
 
 #ifdef WANT_CPU_CRISV3F
 #include "engv3.h"
-#include "cgen-engine.h"
 #include "cpuv3.h"
 #include "decodev3.h"
 #endif
 
 #ifdef WANT_CPU_CRISV8F
 #include "engv8.h"
-#include "cgen-engine.h"
 #include "cpuv8.h"
 #include "decodev8.h"
 #endif
 
 #ifdef WANT_CPU_CRISV10F
 #include "engv10.h"
-#include "cgen-engine.h"
 #include "cpuv10.h"
 #include "decodev10.h"
 #endif
 
 #ifdef WANT_CPU_CRISV32F
 #include "engv32.h"
-#include "cgen-engine.h"
 #include "cpuv32.h"
 #include "decodev32.h"
 #endif
diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h
index 03a1be3..d4d7528 100644
--- a/sim/cris/cpuv10.h
+++ b/sim/cris/cpuv10.h
@@ -32,6 +32,12 @@ This file is part of the GNU simulators.
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h
index 9c575f1..421a5ce 100644
--- a/sim/cris/cpuv32.h
+++ b/sim/cris/cpuv32.h
@@ -32,6 +32,12 @@ This file is part of the GNU simulators.
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c
index 362e8f0..516bb48 100644
--- a/sim/cris/decodev10.c
+++ b/sim/cris/decodev10.c
@@ -316,14 +316,14 @@ crisv10f_init_idesc_table (SIM_CPU *cpu)
 
 const IDESC *
 crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn,
+              CGEN_INSN_WORD base_insn,
               ARGBUF *abuf)
 {
   /* Result of decoder.  */
   CRISV10F_INSN_TYPE itype;
 
   {
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 
     {
       unsigned int val = (((insn >> 4) & (255 << 0)));
@@ -2413,7 +2413,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2441,7 +2441,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_d_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2469,7 +2469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movepcr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_moveq.f
     UINT f_operand2;
 
@@ -2493,7 +2493,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_moveq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_moveq.f
     UINT f_operand2;
     INT f_s6;
@@ -2520,7 +2520,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2548,7 +2548,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -2578,7 +2578,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -2608,7 +2608,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecdr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -2638,7 +2638,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movscbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     UINT f_operand2;
     INT f_indir_pc__byte;
@@ -2668,7 +2668,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movscwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     UINT f_operand2;
     INT f_indir_pc__word;
@@ -2698,7 +2698,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movucbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     UINT f_operand2;
     INT f_indir_pc__byte;
@@ -2728,7 +2728,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movucwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     UINT f_operand2;
     INT f_indir_pc__word;
@@ -2758,7 +2758,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addq.f
     UINT f_operand2;
     UINT f_u6;
@@ -2786,7 +2786,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_r_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2814,7 +2814,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2846,7 +2846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2878,7 +2878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2910,7 +2910,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -2940,7 +2940,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -2970,7 +2970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcdr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -3000,7 +3000,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_andq.f
     UINT f_operand2;
     INT f_s6;
@@ -3027,7 +3027,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpucbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -3057,7 +3057,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpucwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -3087,7 +3087,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3119,7 +3119,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3151,7 +3151,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3183,7 +3183,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3215,7 +3215,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3247,7 +3247,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_sprv10:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3275,7 +3275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_spr_rv10:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3303,7 +3303,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ret_type:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
     UINT f_operand2;
 
@@ -3327,7 +3327,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_sprv10:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3359,7 +3359,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_c_sprv10_p5:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
     UINT f_operand2;
     INT f_indir_pc__word;
@@ -3389,7 +3389,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_c_sprv10_p9:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -3419,7 +3419,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_spr_mv10:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3464,7 +3464,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movem_r_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movem_r_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3512,7 +3512,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movem_m_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3559,7 +3559,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movem_m_pc:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
     UINT f_memmode;
     UINT f_operand1;
@@ -3602,7 +3602,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3631,7 +3631,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_d_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3660,7 +3660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3693,7 +3693,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3726,7 +3726,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3759,7 +3759,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -3790,7 +3790,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -3821,7 +3821,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcdr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcdr.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -3852,7 +3852,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcpc:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
     INT f_indir_pc__dword;
     /* Contents of trailing part of insn.  */
@@ -3878,7 +3878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_adds_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3911,7 +3911,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_adds_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3944,7 +3944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addscbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -3975,7 +3975,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addscwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -4025,7 +4025,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4054,7 +4054,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_neg_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4082,7 +4082,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_neg_d_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4110,7 +4110,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_memmode;
     UINT f_operand1;
@@ -4138,7 +4138,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_memmode;
     UINT f_operand1;
@@ -4166,7 +4166,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_memmode;
     UINT f_operand1;
@@ -4194,7 +4194,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4226,7 +4226,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4258,7 +4258,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4290,7 +4290,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_muls_b:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4320,7 +4320,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mstep:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4349,7 +4349,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dstep:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4378,7 +4378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4407,7 +4407,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_d_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4436,7 +4436,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4469,7 +4469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4502,7 +4502,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4535,7 +4535,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcbr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -4566,7 +4566,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcwr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -4597,7 +4597,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcdr:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcdr.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -4628,7 +4628,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_andq.f
     UINT f_operand2;
     INT f_s6;
@@ -4656,7 +4656,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_swap:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4684,7 +4684,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_asrq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_asrq.f
     UINT f_operand2;
     UINT f_u5;
@@ -4712,7 +4712,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsrr_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4741,7 +4741,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsrr_d_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4770,7 +4770,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btst:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4798,7 +4798,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btstq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_asrq.f
     UINT f_operand2;
     UINT f_u5;
@@ -4825,7 +4825,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_setf:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_setf.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4846,7 +4846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcc_b:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_b.f
     UINT f_operand2;
     UINT f_disp9_lo;
@@ -4882,7 +4882,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ba_b:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_b.f
     UINT f_disp9_lo;
     INT f_disp9_hi;
@@ -4915,7 +4915,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcc_w:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_w.f
     SI f_indir_pc__word_pcrel;
     UINT f_operand2;
@@ -4944,7 +4944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ba_w:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_w.f
     SI f_indir_pc__word_pcrel;
     /* Contents of trailing part of insn.  */
@@ -4970,7 +4970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jump_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4998,7 +4998,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jump_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5030,7 +5030,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jump_c:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -5060,7 +5060,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_break:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_break.f
     UINT f_u4;
 
@@ -5083,7 +5083,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5116,7 +5116,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5149,7 +5149,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5182,7 +5182,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cb:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -5213,7 +5213,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cw:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -5244,7 +5244,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cd:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -5275,7 +5275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_scc:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_operand2;
     UINT f_operand1;
@@ -5302,7 +5302,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addoq:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addoq.f
     UINT f_operand2;
     INT f_s8;
@@ -5329,7 +5329,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bdapqpc:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addoq.f
     INT f_s8;
 
@@ -5352,7 +5352,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bdap_32_pc:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
     INT f_indir_pc__dword;
     /* Contents of trailing part of insn.  */
@@ -5378,7 +5378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_pcplus_p0:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
     UINT f_memmode;
 
@@ -5401,7 +5401,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_spplus_p8:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
     UINT f_memmode;
 
@@ -5426,7 +5426,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_b_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5458,7 +5458,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_w_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5490,7 +5490,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_d_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -5522,7 +5522,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cb:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -5552,7 +5552,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cw:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -5582,7 +5582,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cd:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -5612,7 +5612,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dip_m:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
     UINT f_memmode;
     UINT f_operand1;
@@ -5640,7 +5640,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dip_c:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
     INT f_indir_pc__dword;
     /* Contents of trailing part of insn.  */
@@ -5660,7 +5660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi_acr_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_b_r.f
     UINT f_operand2;
     UINT f_operand1;
@@ -5688,7 +5688,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_biap_pc_b_r:
   {
     const IDESC *idesc = &crisv10f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addoq.f
     UINT f_operand2;
 
diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h
index 11c11fa..8c0f745 100644
--- a/sim/cris/decodev10.h
+++ b/sim/cris/decodev10.h
@@ -26,7 +26,7 @@ This file is part of the GNU simulators.
 #define CRISV10F_DECODE_H
 
 extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT,
+                                  CGEN_INSN_WORD,
                                   ARGBUF *);
 extern void crisv10f_init_idesc_table (SIM_CPU *);
 extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c
index c2ee3a5..5e580d9 100644
--- a/sim/cris/decodev32.c
+++ b/sim/cris/decodev32.c
@@ -320,14 +320,14 @@ crisv32f_init_idesc_table (SIM_CPU *cpu)
 
 const IDESC *
 crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn,
+              CGEN_INSN_WORD base_insn,
               ARGBUF *abuf)
 {
   /* Result of decoder.  */
   CRISV32F_INSN_TYPE itype;
 
   {
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 
     {
       unsigned int val = (((insn >> 4) & (255 << 0)));
@@ -1923,7 +1923,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -1951,7 +1951,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_d_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -1979,7 +1979,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_moveq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_moveq.f
     UINT f_operand2;
     INT f_s6;
@@ -2006,7 +2006,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2034,7 +2034,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -2064,7 +2064,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -2094,7 +2094,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movecdr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -2124,7 +2124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movscbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     UINT f_operand2;
     INT f_indir_pc__byte;
@@ -2154,7 +2154,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movscwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     UINT f_operand2;
     INT f_indir_pc__word;
@@ -2184,7 +2184,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movucbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     UINT f_operand2;
     INT f_indir_pc__byte;
@@ -2214,7 +2214,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movucwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     UINT f_operand2;
     INT f_indir_pc__word;
@@ -2244,7 +2244,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addq.f
     UINT f_operand2;
     UINT f_u6;
@@ -2272,7 +2272,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_r_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2300,7 +2300,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2332,7 +2332,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2364,7 +2364,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2396,7 +2396,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -2426,7 +2426,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -2456,7 +2456,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpcdr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -2486,7 +2486,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_andq.f
     UINT f_operand2;
     INT f_s6;
@@ -2513,7 +2513,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpucbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -2543,7 +2543,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpucwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -2573,7 +2573,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2605,7 +2605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2637,7 +2637,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2669,7 +2669,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2701,7 +2701,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movs_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2733,7 +2733,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_sprv32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2761,7 +2761,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_spr_rv32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mcp.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2789,7 +2789,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_m_sprv32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2821,7 +2821,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_c_sprv32_p2:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -2851,7 +2851,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_spr_mv32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2883,7 +2883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_ss_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2910,7 +2910,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_ss:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mcp.f
     UINT f_operand2;
     UINT f_operand1;
@@ -2937,7 +2937,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movem_r_m_v32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
     UINT f_operand2;
     UINT f_memmode;
@@ -2985,7 +2985,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movem_m_r_v32:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3033,7 +3033,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3062,7 +3062,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_d_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3091,7 +3091,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3124,7 +3124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3157,7 +3157,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3190,7 +3190,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -3221,7 +3221,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -3252,7 +3252,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addcdr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcdr.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -3283,7 +3283,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_adds_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3316,7 +3316,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_adds_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3349,7 +3349,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addscbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -3380,7 +3380,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addscwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -3411,7 +3411,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addc_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3444,7 +3444,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lapc_d:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_lapc_d.f
     SI f_indir_pc__dword_pcrel;
     UINT f_operand2;
@@ -3474,7 +3474,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lapcq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_lapcq.f
     UINT f_operand2;
     SI f_qo;
@@ -3501,7 +3501,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3530,7 +3530,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_neg_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3558,7 +3558,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_neg_d_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3586,7 +3586,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_memmode;
     UINT f_operand1;
@@ -3614,7 +3614,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_memmode;
     UINT f_operand1;
@@ -3642,7 +3642,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_test_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_memmode;
     UINT f_operand1;
@@ -3670,7 +3670,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3702,7 +3702,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3734,7 +3734,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_move_r_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3766,7 +3766,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_muls_b:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3796,7 +3796,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mcp:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mcp.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3825,7 +3825,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dstep:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3854,7 +3854,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3883,7 +3883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_d_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -3912,7 +3912,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3945,7 +3945,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -3978,7 +3978,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4011,7 +4011,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcbr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcbr.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -4042,7 +4042,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcwr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcwr.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -4073,7 +4073,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andcdr:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addcdr.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -4104,7 +4104,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_andq.f
     UINT f_operand2;
     INT f_s6;
@@ -4132,7 +4132,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_swap:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4160,7 +4160,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_asrq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_asrq.f
     UINT f_operand2;
     UINT f_u5;
@@ -4188,7 +4188,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsrr_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4217,7 +4217,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsrr_d_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4246,7 +4246,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btst:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4274,7 +4274,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btstq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_asrq.f
     UINT f_operand2;
     UINT f_u5;
@@ -4301,7 +4301,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_setf:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_setf.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4423,7 +4423,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcc_b:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_b.f
     UINT f_operand2;
     UINT f_disp9_lo;
@@ -4459,7 +4459,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ba_b:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_b.f
     UINT f_disp9_lo;
     INT f_disp9_hi;
@@ -4492,7 +4492,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcc_w:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_w.f
     SI f_indir_pc__word_pcrel;
     UINT f_operand2;
@@ -4521,7 +4521,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ba_w:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bcc_w.f
     SI f_indir_pc__word_pcrel;
     /* Contents of trailing part of insn.  */
@@ -4547,7 +4547,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jas_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4575,7 +4575,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jas_c:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -4605,7 +4605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jump_p:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mcp.f
     UINT f_operand2;
 
@@ -4629,7 +4629,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bas_c:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bas_c.f
     SI f_indir_pc__dword_pcrel;
     UINT f_operand2;
@@ -4659,7 +4659,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jasc_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4687,7 +4687,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_break:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_break.f
     UINT f_u4;
 
@@ -4710,7 +4710,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cb:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -4741,7 +4741,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cw:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -4772,7 +4772,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bound_cd:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -4803,7 +4803,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_scc:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
     UINT f_operand2;
     UINT f_operand1;
@@ -4830,7 +4830,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addoq:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addoq.f
     UINT f_operand2;
     INT f_s8;
@@ -4857,7 +4857,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_b_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4889,7 +4889,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_w_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4921,7 +4921,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_m_d_m:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addc_m.f
     UINT f_operand2;
     UINT f_memmode;
@@ -4953,7 +4953,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cb:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cb.f
     INT f_indir_pc__byte;
     UINT f_operand2;
@@ -4983,7 +4983,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cw:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cw.f
     INT f_indir_pc__word;
     UINT f_operand2;
@@ -5013,7 +5013,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addo_cd:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_bound_cd.f
     INT f_indir_pc__dword;
     UINT f_operand2;
@@ -5043,7 +5043,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi_acr_b_r:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_muls_b.f
     UINT f_operand2;
     UINT f_operand1;
@@ -5071,7 +5071,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_fidxi:
   {
     const IDESC *idesc = &crisv32f_insn_data[itype];
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mcp.f
     UINT f_operand1;
 
diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h
index 78a90e2..6eac53e 100644
--- a/sim/cris/decodev32.h
+++ b/sim/cris/decodev32.h
@@ -26,7 +26,7 @@ This file is part of the GNU simulators.
 #define CRISV32F_DECODE_H
 
 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT,
+                                  CGEN_INSN_WORD,
                                   ARGBUF *);
 extern void crisv32f_init_idesc_table (SIM_CPU *);
 extern void crisv32f_sem_init_idesc_table (SIM_CPU *);