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author | Hans-Peter Nilsson <hp@axis.com> | 2006-04-03 03:01:45 +0000 |
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committer | Hans-Peter Nilsson <hp@axis.com> | 2006-04-03 03:01:45 +0000 |
commit | aad3b3cbc1391fb0091d03b252bd53fbd1d2dd84 (patch) | |
tree | d084f6526cd6241af91f2bb5c097a86b07a71a87 /sim/cris/crisv10f.c | |
parent | 4c3a323bb9b03802339b28311c228a5152829474 (diff) | |
download | gdb-aad3b3cbc1391fb0091d03b252bd53fbd1d2dd84.zip gdb-aad3b3cbc1391fb0091d03b252bd53fbd1d2dd84.tar.gz gdb-aad3b3cbc1391fb0091d03b252bd53fbd1d2dd84.tar.bz2 |
* cris/dv-cris.c, cris/dv-rv.c, cris/rvdummy.c: New files.
* cris/Makefile.in (CONFIG_DEVICES): Remove redundant setting.
(dv-cris.o, dv-rv.o rvdummy$(EXEEXT), rvdummy.o): New rules.
(all): Depend on rvdummy$(EXEEXT).
* cris/configure.ac: Call SIM_AC_OPTION_WARNINGS. Check for
sys/socket.h and sys/select.h. Call SIM_AC_OPTION_HARDWARE,
default off.
* cris/configure: Regenerate.
* cris/cris-sim.h (cris_have_900000xxif): Declare here.
(enum cris_interrupt_type, crisv10deliver_interrupt)
(crisv32deliver_interrupt: New declarations.
* cris/cris-tmpl.c [WITH_HW] (MY (f_model_insn_after)): Call
sim_events_tickn and set state-events member work_pending when it's
time for the next event.
[WITH_HW] (MY (f_specific_init)): Set CPU-model-specific
interrupt-delivery function.
* cris/crisv10f.c (MY (deliver_interrupt)): New function.
* cris/crisv32f.c (MY (deliver_interrupt)): New function.
* cris/devices.c: Include hw-device.h.
(device_io_read_buffer) [WITH_HW]: Call hw_io_read_buffer.
(device_io_write_buffer): Only perform 0x900000xx-functions if
cris_have_900000xxif is nonzero. Else if WITH_HW defined,
call hw_io_write_buffer. Add return 0 last in function.
* cris/sim-if.c (cris_have_900000xxif): Now global.
(sim_open) [WITH_HW]: Clear deliver_interrupt cpu member.
Force "-model" option, effectively.
* cris/sim-main.h (cris_interrupt_delivery_fn): New type.
(struct _sim_cpu) [WITH_HW]: New member deliver_interrupt.
Diffstat (limited to 'sim/cris/crisv10f.c')
-rw-r--r-- | sim/cris/crisv10f.c | 61 |
1 files changed, 60 insertions, 1 deletions
diff --git a/sim/cris/crisv10f.c b/sim/cris/crisv10f.c index 0c2a17c..976badb 100644 --- a/sim/cris/crisv10f.c +++ b/sim/cris/crisv10f.c @@ -1,5 +1,5 @@ /* CRIS v10 simulator support code - Copyright (C) 2004, 2005 Free Software Foundation, Inc. + Copyright (C) 2004, 2005, 2006 Free Software Foundation, Inc. Contributed by Axis Communications. This file is part of the GNU simulators. @@ -40,3 +40,62 @@ MY (XCONCAT3 (f_model_crisv,BASENUM, } #endif /* WITH_PROFILE_MODEL_P */ + +/* Do the interrupt sequence if possible, and return 1. If interrupts + are disabled or some other lockout is active, return 0 and do + nothing. + + Beware, the v10 implementation is incomplete and doesn't properly + lock out interrupts e.g. after special-register access and doesn't + handle user-mode. */ + +int +MY (deliver_interrupt) (SIM_CPU *current_cpu, + enum cris_interrupt_type type, + unsigned int vec) +{ + unsigned char entryaddr_le[4]; + int was_user; + SIM_DESC sd = CPU_STATE (current_cpu); + unsigned32 entryaddr; + + /* We haven't implemented other interrupt-types yet. */ + if (type != CRIS_INT_INT) + abort (); + + /* We're supposed to be called outside of prefixes and branch + delay-slots etc, but why not check. */ + if (GET_H_INSN_PREFIXED_P ()) + abort (); + + if (!GET_H_IBIT ()) + return 0; + + /* User mode isn't supported for interrupts. (And we shouldn't see + this as 1 anyway. The user-mode bit isn't visible from user + mode. It doesn't make it into the U bit until the next + interrupt/exception.) */ + if (GET_H_UBIT ()) + abort (); + + SET_H_PBIT (1); + + if (sim_core_read_buffer (sd, + current_cpu, + read_map, entryaddr_le, + GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0) + { + /* Nothing to do actually; either abort or send a signal. */ + sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4, + GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, + read_transfer, sim_core_unmapped_signal); + return 0; + } + + entryaddr = bfd_getl32 (entryaddr_le); + + SET_H_SR (H_SR_PRE_V32_IRP, GET_H_PC ()); + SET_H_PC (entryaddr); + + return 1; +} |