sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.

1 files changed, 8 insertions, 0 deletions

diff --git a/sim/configure b/sim/configure
index 28ed5d7..1f1ce75 100755
--- a/sim/configure
+++ b/sim/configure
@@ -690,6 +690,7 @@ moxie
 msp430
 or1k
 pru
+riscv
 rl78
 rx
 sh
@@ -4029,6 +4030,13 @@ subdirs="$subdirs aarch64"
 
 
        ;;
+   riscv*-*-*)
+
+  sim_arch=riscv
+  subdirs="$subdirs riscv"
+
+
+       ;;
    rl78-*-*)
 
   sim_arch=rl78