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| author | Stafford Horne <shorne@gmail.com> | 2017-12-09 05:57:25 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-12-12 23:44:14 +0900 |
| commit | fa8b7c2128cd03135b7d31ae2ecbc2d3273e990d (patch) | |
| tree | a8014af075efa262869a91c4114ab4adb0e20d68 /sim/configure.tgt | |
| parent | 58884b0e451043ed2fb4d2fba18134f0fb451ce5 (diff) | |
| download | gdb-fa8b7c2128cd03135b7d31ae2ecbc2d3273e990d.zip gdb-fa8b7c2128cd03135b7d31ae2ecbc2d3273e990d.tar.gz gdb-fa8b7c2128cd03135b7d31ae2ecbc2d3273e990d.tar.bz2 | |
sim: or1k: add or1k target to sim
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN
based sim so the bulk of the code is generated from the .cpu files by
CGEN. The engine decode and execute logic in mloop uses scache with
pseudo-basic-block extraction and supports both full and fast (switch)
modes.
The sim does not implement an mmu at the moment. The sim does implement
fpu instructions via the common sim-fpu implementation.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure.tgt: Add or1k sim.
* or1k/README: New file.
* or1k/Makefile.in: New file.
* or1k/configure.ac: New file.
* or1k/mloop.in: New file.
* or1k/or1k-sim.h: New file.
* or1k/or1k.c: New file.
* or1k/sim-if.c: New file.
* or1k/sim-main.h: New file.
* or1k/traps.c: New file.
Diffstat (limited to 'sim/configure.tgt')
| -rw-r--r-- | sim/configure.tgt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sim/configure.tgt b/sim/configure.tgt index c958fb3..a6dbd1a 100644 --- a/sim/configure.tgt +++ b/sim/configure.tgt @@ -76,6 +76,9 @@ case "${target}" in msp430*-*-*) SIM_ARCH(msp430) ;; + or1k-*-* | or1knd-*-*) + SIM_ARCH(or1k) + ;; rl78-*-*) SIM_ARCH(rl78) ;; |