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| author | Ben Elliston <bje@au.ibm.com> | 2001-07-05 13:51:26 +0000 |
|---|---|---|
| committer | Ben Elliston <bje@au.ibm.com> | 2001-07-05 13:51:26 +0000 |
| commit | e3e473dacce6cbb004fe94f0dba60955ac1018f2 (patch) | |
| tree | 756895f478098ca36f74d3306f1cdd1b82e83e92 /sim/common | |
| parent | 4a3264e6a1370cbae94d8fd11402617dbc7dbe1b (diff) | |
| download | gdb-e3e473dacce6cbb004fe94f0dba60955ac1018f2.zip gdb-e3e473dacce6cbb004fe94f0dba60955ac1018f2.tar.gz gdb-e3e473dacce6cbb004fe94f0dba60955ac1018f2.tar.bz2 | |
2001-07-05 Ben Elliston <bje@redhat.com>
* Make-common.in (srccgen): Remove.
(CGEN_CPU_DIR): Define.
(CGEN_READ_SCM): Redefine without $(srccgen).
(CGEN_ARCH_SCM): Ditto.
(CGEN_CPU_SCM): Ditto.
(CGEN_DECODE_SCM): Ditto.
(CGEN_DESC_SCM): Ditto.
* $arch/Makefile.in: Use $(CGEN_CPU_DIR) where applicable.
Diffstat (limited to 'sim/common')
| -rw-r--r-- | sim/common/ChangeLog | 10 | ||||
| -rw-r--r-- | sim/common/Make-common.in | 14 |
2 files changed, 17 insertions, 7 deletions
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 1117307..0b94177 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,13 @@ +2001-07-05 Ben Elliston <bje@redhat.com> + + * Make-common.in (srccgen): Remove. + (CGEN_CPU_DIR): Define. + (CGEN_READ_SCM): Redefine without $(srccgen). + (CGEN_ARCH_SCM): Ditto. + (CGEN_CPU_SCM): Ditto. + (CGEN_DECODE_SCM): Ditto. + (CGEN_DESC_SCM): Ditto. + 2001-04-25 Frank Ch. Eigler <fche@redhat.com> * sim-load.c (sim_load_file): Put it back: external now. diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in index f37d03f..519b213 100644 --- a/sim/common/Make-common.in +++ b/sim/common/Make-common.in @@ -1,5 +1,5 @@ # Makefile fragment for common parts of all simulators. -# Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +# Copyright 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. # Contributed by Cygnus Support. # This program is free software; you can redistribute it and/or modify @@ -659,13 +659,13 @@ stamp-h: config.in config.status CGENDIR = @cgendir@ CGEN = `if [ -f ../../guile/libguile/guile ]; then echo ../../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -srccgen = $(CGENDIR) +CGEN_CPU_DIR = $(CGENDIR)/cpu -CGEN_READ_SCM = ../../cgen/stamp-cgen $(srccgen)/sim.scm -CGEN_ARCH_SCM = $(srccgen)/sim-arch.scm -CGEN_CPU_SCM = $(srccgen)/sim-cpu.scm $(srccgen)/sim-model.scm -CGEN_DECODE_SCM = $(srccgen)/sim-decode.scm -CGEN_DESC_SCM = $(srccgen)/desc.scm $(srccgen)/desc-cpu.scm +CGEN_READ_SCM = ../../cgen/stamp-cgen $(CGENDIR)/sim.scm +CGEN_ARCH_SCM = $(CGENDIR)/sim-arch.scm +CGEN_CPU_SCM = $(CGENDIR)/sim-cpu.scm $(CGENDIR)/sim-model.scm +CGEN_DECODE_SCM = $(CGENDIR)/sim-decode.scm +CGEN_DESC_SCM = $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm # Various choices for which cpu specific files to generate. CGEN_CPU_EXTR = -E tmp-ext.c1 |