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authorDoug Evans <dje@google.com>1998-10-09 22:43:05 +0000
committerDoug Evans <dje@google.com>1998-10-09 22:43:05 +0000
commit0b517b9cf2f539c9951f619fbd15d4231cf2416b (patch)
treee9de00e890900c63bc5c4c20374b9f9d89d3e768 /sim/common
parent60fc3193fc983810b1d8500d64973283350415f0 (diff)
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* Make-common.in (sim-reg.o): New rule.
(cgen-run.o): New rule. * cgen-ops.h: Delete many BI macros. Change all UBI -> BI. * cgen-run.c (prime_cpu): New function. * cgen-scache.c: Add pseudo-basic-block (pbb) scaching support. (scache_option_handler, case OPTION_PROFILE_SCACHE): Handle explicitly mentioned cpu. (scache_flush_cpu,scache_lookup,scache_lookup_or_alloc): New fns. * cgen-sim.h (CGEN_INSN_VIRTUAL_TYPE): New enum. (CGEN_INSN_VIRTUAL_P): New macro. (SEM_PC): New typedef. (SEMANTIC_FN): Change type of result to SEM_PC. (SEM_SET_FULL_CODE,SEM_SET_FAST_CODE,SEM_SET_CODE): New macros. (IDESC_CTI_P,IDESC_SKIP_P): New macros. (SCACHE_MAP): New typedef. (CPU_SCACHE): Add pbb support. (scace_lookup,scache_lookup_or_alloc,scache_flush_cpu): Declare. (SEM_BRANCH_INIT_EXTRACT,SEM_BRANCH_INIT,SEM_BRANCH_FINI): New macros. (CGEN_CPU): New members running_p,insn_count,{fast,full}_engine_fn, max_slice_insns. (INSN_NAME): Delete. (cgen_insn_name): Declare. (sim_engine_invalid_insn): Renamed from sim_engine_illegal_insn. * cgen-trace.c (trace_buf): Shrink from 1024 to 256 bytes. (first_insn_p): Make static. (trace_insn): Handle virtual insns specially. (cgen_trace_printf): Ensure we haven't overflowed the buffer. * cgen-types.h (UBI): Delete. (MODE_TYPE): New enum. (HOSTINT,HOSTUINT,HOSTPTR): Delete. * cgen-utils.c (mode_names): Delete UBI. Add INT,UINT,PTR. (cgen_virtual_opcode_table): New global. (cgen_insn_name): New function. (sim_disassemble_insn): Ignore virtual insns. * genmloop.sh: Delete top level loop generation. Add pbb support. * sim-cpu.h (CPU_INSN_NAME_FN): New typedef. (sim_cpu_base): New members max_insns,insn_name,model_data. (CPU_PC_GET,CPU_PC_SET): New macros. (sim_pc_get,sim_pc_set): Declare. * sim-model.c (model_set): Call model init fn. * sim-model.h (MODEL_FN): New typedef. (INSN_TIMING): New member model_fn. (MODEL): New members num,init. * sim-profile.c (sim_profile_print_bar): Renamed from print_bar. All callers updated. (profile_insn_init): New fn. (profile_print_insn): Update, INSN_NAME -> CPU_INSN_NAME. Exit early if insn profiling not supported. (profile_print_memory): Update, MAX_MODES -> MODE_TARGET_MAX. (profile_install): Record profile_insn_init as init fn. (profile_uninstall): Free PROFILE_INSN_COUNT if non-null. * sim-profile.h: Update, MAX_MODES -> MODE_TARGET_MAX. (PROFILE_DATA): Delete member exec_time. Change insn_count to pointer to array, rather than the array. (sim_profile_print_bar): Declare.
Diffstat (limited to 'sim/common')
-rw-r--r--sim/common/sim-cpu.h147
1 files changed, 147 insertions, 0 deletions
diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h
new file mode 100644
index 0000000..f8996f5
--- /dev/null
+++ b/sim/common/sim-cpu.h
@@ -0,0 +1,147 @@
+/* CPU support.
+ Copyright (C) 1998 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* This file is intended to be included by sim-base.h.
+
+ This file provides an interface between the simulator framework and
+ the selected cpu. */
+
+#ifndef SIM_CPU_H
+#define SIM_CPU_H
+
+/* Type of function to return an insn name. */
+typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
+
+/* Types for register access functions.
+ These routines implement the sim_{fetch,store}_register interface. */
+typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
+typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int);
+
+/* Types for PC access functions.
+ Some simulators require a functional interface to access the program
+ counter [a macro is insufficient as the PC is kept in a cpu-specific part
+ of the sim_cpu struct]. */
+typedef sim_cia (PC_FETCH_FN) (sim_cpu *);
+typedef void (PC_STORE_FN) (sim_cpu *, sim_cia);
+
+/* Pseudo baseclass for each cpu. */
+
+typedef struct {
+
+ /* Backlink to main state struct. */
+ SIM_DESC state;
+#define CPU_STATE(cpu) ((cpu)->base.state)
+
+ /* Processor index within the SD_DESC */
+ int index;
+#define CPU_INDEX(cpu) ((cpu)->base.index)
+
+ /* The name of the cpu. */
+ const char *name;
+#define CPU_NAME(cpu) ((cpu)->base.name)
+
+ /* Options specific to this cpu. */
+ struct option_list *options;
+#define CPU_OPTIONS(cpu) ((cpu)->base.options)
+
+ /* Processor specific core data */
+ sim_cpu_core core;
+#define CPU_CORE(cpu) (& (cpu)->base.core)
+
+ /* Number of instructions (used to iterate over CPU_INSN_NAME). */
+ unsigned int max_insns;
+#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns)
+
+ /* Function to return the name of an insn. */
+ CPU_INSN_NAME_FN *insn_name;
+#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name)
+
+ /* Trace data. See sim-trace.h. */
+ TRACE_DATA trace_data;
+#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
+
+ /* Maximum number of debuggable entities.
+ This debugging is not intended for normal use.
+ It is only enabled when the simulator is configured with --with-debug
+ which shouldn't normally be specified. */
+#ifndef MAX_DEBUG_VALUES
+#define MAX_DEBUG_VALUES 4
+#endif
+
+ /* Boolean array of specified debugging flags. */
+ char debug_flags[MAX_DEBUG_VALUES];
+#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
+ /* Standard values. */
+#define DEBUG_INSN_IDX 0
+#define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
+
+ /* Debugging output goes to this or stderr if NULL.
+ We can't store `stderr' here as stderr goes through a callback. */
+ FILE *debug_file;
+#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
+
+ /* Profile data. See sim-profile.h. */
+ PROFILE_DATA profile_data;
+#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
+
+#ifdef SIM_HAVE_MODEL
+ /* Machine tables for this cpu. See sim-model.h. */
+ const MACH *mach;
+#define CPU_MACH(cpu) ((cpu)->base.mach)
+ /* The selected model. */
+ const MODEL *model;
+#define CPU_MODEL(cpu) ((cpu)->base.model)
+ /* Model data (profiling state, etc.). */
+ void *model_data;
+#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data)
+#endif
+
+ /* Routines to fetch/store registers. */
+ CPUREG_FETCH_FN *reg_fetch;
+#define CPU_REG_FETCH(c) ((c)->base.reg_fetch)
+ CPUREG_STORE_FN *reg_store;
+#define CPU_REG_STORE(c) ((c)->base.reg_store)
+ PC_FETCH_FN *pc_fetch;
+#define CPU_PC_FETCH(c) ((c)->base.pc_fetch)
+ PC_STORE_FN *pc_store;
+#define CPU_PC_STORE(c) ((c)->base.pc_store)
+
+} sim_cpu_base;
+
+/* Create all cpus. */
+extern SIM_RC sim_cpu_alloc_all (SIM_DESC, int, int);
+/* Create a cpu. */
+extern sim_cpu *sim_cpu_alloc (SIM_DESC, int);
+/* Release resources held by all cpus. */
+extern void sim_cpu_free_all (SIM_DESC);
+/* Release resources held by a cpu. */
+extern void sim_cpu_free (sim_cpu *);
+
+/* Return a pointer to the cpu data for CPU_NAME, or NULL if not found. */
+extern sim_cpu *sim_cpu_lookup (SIM_DESC, const char *);
+
+/* Get/set a pc value. */
+#define CPU_PC_GET(cpu) ((* CPU_PC_FETCH (cpu)) (cpu))
+#define CPU_PC_SET(cpu,newval) ((* CPU_PC_STORE (cpu)) ((cpu), (newval)))
+/* External interface to accessing the pc. */
+sim_cia sim_pc_get (sim_cpu *);
+void sim_pc_set (sim_cpu *, sim_cia);
+
+#endif /* SIM_CPU_H */