* Make-common.in (cgen-{arch,cpu,decode}): New targets.

	* cgen.sh: New file.
	* cgen-scache.h: Deleted.
	* cgen-scache.c: Only compile contents if WITH_SCACHE.
	(scache_init): Use runtime computed size of SCACHE.
	(scache_flush): Likewise.
	* cgen-mem.h (GETIMEMU[QHSD]I): Declare.
	([GS]ETT{QI,UQI,HI,UHI,SI,USI,DI,UDI}): Declare.
	* cgen-sim.h: Scache support moved here.
	(PC): Redo definition.
	(ARGBUF,SCACHE,PARALLEL_EXEC): Provide forward decls.
	(DECODE): Add parallel execution support.
	Only include semantic label members if using switch.
	(SWITCH,CASE,BREAK,DEFAULT,ENDSWITCH): Portable computed goto support.
	(CGEN_CPU): Delete members exec_state, halt_sigrc, halt_jmp_buf.
	(IADDR,CIA,SEM_ARG,EX_FN_NAME,SEM_FN_NAME,RECORD_IADDR,SEM_ARGBUF,
	SEM_NEXT_PC,SEM_BRANCH_VIA_{CACHE,ADDR},SEM_NEW_PC_ADDR): Moved here
	from cgen-types.h.
	(engine_{stop,run,resume,halt,signal}): Delete decls.
	* cgen-types.h (CGEN_{XCAT3,CAT3}): Delete.
	(argbuf,scache): Delete forward decls.
	(STATE): Delete decl.
	* cgen-utils.c: Don't include decode.h, mem-ops.h, sem-ops.h.
	Include cgen-mem.h, cgen-ops.h.
	(engine_halt,engine_signal): Delete.
	({ex,exc,sem,semc}_illegal): Delete.
	(sim_disassemble_insn): Result of extract fn is in bits.
	* genmloop.sh: Rewrite.

1 files changed, 50 insertions, 2 deletions

diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in
index fb1cf8f..9ed1bb3 100644
--- a/sim/common/Make-common.in
+++ b/sim/common/Make-common.in
@@ -300,10 +300,11 @@ sim-bits.o: $(srccom)/sim-bits.c $(sim-bits_h) $(sim-n-bits_h) \
 	$(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS)
 
 sim-config.o: $(srccom)/sim-config.c $(sim-config_h) \
-	$(SIM_EXTRA_DEPS)
+	  $(SIM_EXTRA_DEPS)
 	$(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS)
 
-sim-core.o: $(srccom)/sim-core.c $(sim-core_h) $(sim-n-core_h) \
+sim-core.o: $(srccom)/sim-core.c $(sim_main_headers) \
+	  $(sim-core_h) $(sim-n-core_h) \
 	  $(SIM_EXTRA_DEPS)
 	$(CC) -c $(srccom)/sim-core.c $(ALL_CFLAGS)
 
@@ -478,4 +479,51 @@ stamp-h: config.in config.status
 .gdbinit: # config.status $(srccom)/gdbinit.in
 	CONFIG_FILES=$@:../common/gdbinit.in CONFIG_HEADERS= $(SHELL) ./config.status
 
+# CGEN support
+
+SCHEME = @SCHEME@
+SCHEME = guile-ss
+SCHEME = guile
+#SCHEMEFLAGS = -b
+SCHEMEFLAGS = -s
+srccgen = $(srcroot)/cgen
+
+CGEN_VERBOSE = -v
+CGEN_MAIN_SCM = $(srccgen)/object.scm \
+	$(srccgen)/utils.scm $(srccgen)/utils-cgen.scm \
+	$(srccgen)/mode.scm \
+	$(srccgen)/cpu.scm $(srccgen)/mach.scm \
+	$(srccgen)/ifield.scm $(srccgen)/iformat.scm \
+	$(srccgen)/operand.scm $(srccgen)/insn.scm \
+	$(srccgen)/sim.scm
+CGEN_CPU_SCM = $(srccgen)/sim-cpu.scm $(srccgen)/sem-ccode.scm
+CGEN_DECODE_SCM = $(srccgen)/decode.scm
+
+# Various choices for which cpu specific files to generate.
+CGEN_CPU_EXTR = -E tmp-ext.c1
+CGEN_CPU_READ = -R tmp-read.c1
+CGEN_CPU_SEM = -S tmp-sem.c1
+CGEN_CPU_SEMSW = -W tmp-semsw.c1
+
+# We store the generated files in the source directory until we decide to
+# ship a Scheme interpreter with gdb/binutils.  Maybe we never will.
+
+cgen-arch: force
+	$(SHELL) $(srccom)/cgen.sh arch $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" ignored ignored ignored ignored
+
+cgen-cpu: force
+	$(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" "$(EXTRAFILES)"
+
+cgen-decode: force
+	$(SHELL) $(srccom)/cgen.sh decode $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" ignored
+
 ## End COMMON_POST_CONFIG_FRAG