diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-06-18 22:03:10 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-06-18 22:03:10 +0000 |
| commit | 1f20b1457b31ca6925063318467fec344a236de3 (patch) | |
| tree | cc049b5c3954aa305de6f9939121518624693913 /sim/bfin | |
| parent | b4876e0485f5d16a5d9e213c0b15466323170cf0 (diff) | |
| download | gdb-1f20b1457b31ca6925063318467fec344a236de3.zip gdb-1f20b1457b31ca6925063318467fec344a236de3.tar.gz gdb-1f20b1457b31ca6925063318467fec344a236de3.tar.bz2 | |
sim: bfin: set ASTAT AV/AVS when shifting accumulators overflow
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS
handling in the ASTAT register, so add it to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin')
| -rw-r--r-- | sim/bfin/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/bfin/bfin-sim.c | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 8fd629a..92d968a 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,5 +1,11 @@ 2011-06-18 Robin Getz <robin.getz@analog.com> + * bfin-sim.c (decode_dsp32shift_0): Clear ASTAT[AV] if val is 0, + else set it. Set ASTAT[AVS] if val is 0. Do this for LSHIFT and + ASHIFT accumulator insns. + +2011-06-18 Robin Getz <robin.getz@analog.com> + * bfin-sim.c (ashiftrt): If size is 40, do not call SET_ASTATREG. (lshiftrt): Likewise. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index dbfce6c..fe4dc26 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -5223,6 +5223,9 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) STORE (AXREG (HLs), (val >> 32) & 0xff); STORE (AWREG (HLs), (val & 0xffffffff)); + STORE (ASTATREG (av[HLs]), val == 0); + if (val == 0) + STORE (ASTATREG (avs[HLs]), 1); } else if (sop == 1 && sopcde == 3 && (HLs == 0 || HLs == 1)) { @@ -5240,6 +5243,9 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) STORE (AXREG (HLs), (val >> 32) & 0xff); STORE (AWREG (HLs), (val & 0xffffffff)); + STORE (ASTATREG (av[HLs]), val == 0); + if (val == 0) + STORE (ASTATREG (avs[HLs]), 1); } else if ((sop == 0 || sop == 1) && sopcde == 1) { |