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| author | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 12:54:19 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 12:54:19 +0000 |
| commit | f2db709f4f9df667bb92816511bafd91636c46fd (patch) | |
| tree | 1fca6804e83f0f17df921235a409e0c0bb14ff06 /sim/bfin/machs.h | |
| parent | c43aadcaa6c1b7f5c853276b347fd46f67e8ba09 (diff) | |
| download | gdb-f2db709f4f9df667bb92816511bafd91636c46fd.zip gdb-f2db709f4f9df667bb92816511bafd91636c46fd.tar.gz gdb-f2db709f4f9df667bb92816511bafd91636c46fd.tar.bz2 | |
sim: bfin: move model data into machs.h
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header. The models themselves don't care about
where they're mapped, only the mach code does. This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding. Such as when a newer device model is
created, but with incompatible register names/layouts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/machs.h')
| -rw-r--r-- | sim/bfin/machs.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/sim/bfin/machs.h b/sim/bfin/machs.h index ac16adb..1723ded 100644 --- a/sim/bfin/machs.h +++ b/sim/bfin/machs.h @@ -53,4 +53,51 @@ enum { BFIN_INSN_MAX }; +#define BFIN_COREMMR_CEC_BASE 0xFFE02100 +#define BFIN_COREMMR_CEC_SIZE (4 * 5) +#define BFIN_COREMMR_CTIMER_BASE 0xFFE03000 +#define BFIN_COREMMR_CTIMER_SIZE (4 * 4) +#define BFIN_COREMMR_EVT_BASE 0xFFE02000 +#define BFIN_COREMMR_EVT_SIZE (4 * 16) +#define BFIN_COREMMR_JTAG_BASE 0xFFE05000 +#define BFIN_COREMMR_JTAG_SIZE (4 * 3) +#define BFIN_COREMMR_MMU_BASE 0xFFE00000 +#define BFIN_COREMMR_MMU_SIZE 0x2000 +#define BFIN_COREMMR_PFMON_BASE 0xFFE08000 +#define BFIN_COREMMR_PFMON_SIZE 0x108 +#define BFIN_COREMMR_TRACE_BASE 0xFFE06000 +#define BFIN_COREMMR_TRACE_SIZE (4 * 65) +#define BFIN_COREMMR_WP_BASE 0xFFE07000 +#define BFIN_COREMMR_WP_SIZE 0x204 + +#define BFIN_MMR_DMA_SIZE (4 * 16) +#define BFIN_MMR_DMAC0_BASE 0xFFC00C00 +#define BFIN_MMR_DMAC1_BASE 0xFFC01C00 +#define BFIN_MMR_EBIU_AMC_SIZE (4 * 3) +#define BF50X_MMR_EBIU_AMC_SIZE 0x28 +#define BF54X_MMR_EBIU_AMC_SIZE (4 * 7) +#define BFIN_MMR_EBIU_DDRC_SIZE 0xb0 +#define BFIN_MMR_EBIU_SDC_SIZE (4 * 4) +#define BFIN_MMR_EMAC_BASE 0xFFC03000 +#define BFIN_MMR_EMAC_SIZE 0x200 +#define BFIN_MMR_EPPI_SIZE 0x40 +#define BFIN_MMR_GPIO_SIZE (17 * 4) +#define BFIN_MMR_GPTIMER_SIZE (4 * 4) +#define BFIN_MMR_NFC_SIZE 0x50 +/* XXX: Not exactly true; it's two sets of 4 regs near each other: + 0xFFC03600 0x10 - Control + 0xFFC03680 0x10 - Data */ +#define BFIN_MMR_OTP_SIZE 0xa0 +#define BFIN_MMR_PLL_BASE 0xFFC00000 +#define BFIN_MMR_PLL_SIZE (4 * 6) +#define BFIN_MMR_PPI_SIZE (4 * 5) +#define BFIN_MMR_RTC_SIZE (4 * 6) +#define BFIN_MMR_SIC_BASE 0xFFC00100 +#define BFIN_MMR_SIC_SIZE 0x100 +#define BFIN_MMR_SPI_SIZE (4 * 7) +#define BFIN_MMR_TWI_SIZE 0x90 +#define BFIN_MMR_WDOG_SIZE (4 * 3) +#define BFIN_MMR_UART_SIZE 0x30 +#define BFIN_MMR_UART2_SIZE 0x30 + #endif |