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| author | Mike Frysinger <vapier@gentoo.org> | 2011-06-22 04:21:29 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-06-22 04:21:29 +0000 |
| commit | ce2486ab207e98f04931bc0f562ed4807258344a (patch) | |
| tree | cacfd146f48a530c740e31365d6506db9d32f706 /sim/bfin/interp.c | |
| parent | 8eebce8e670072393bc64915348029d68238eee2 (diff) | |
| download | gdb-ce2486ab207e98f04931bc0f562ed4807258344a.zip gdb-ce2486ab207e98f04931bc0f562ed4807258344a.tar.gz gdb-ce2486ab207e98f04931bc0f562ed4807258344a.tar.bz2 | |
sim: bfin: pass up result2/errcode with libgloss syscalls
Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/interp.c')
| -rw-r--r-- | sim/bfin/interp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c index d0a4e22..583b82e 100644 --- a/sim/bfin/interp.c +++ b/sim/bfin/interp.c @@ -594,8 +594,8 @@ bfin_syscall (SIM_CPU *cpu) { tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode); SET_DREG (0, sc.result); - /* Blackfin libgloss only expects R0 to be updated, not R1. */ - /*SET_DREG (1, sc.errcode);*/ + SET_DREG (1, sc.result2); + SET_DREG (2, sc.errcode); } TRACE_SYSCALL (cpu, "%s", _tbuf); |