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| author | Tristan Gingold <gingold@adacore.com> | 2009-11-09 13:50:30 +0000 |
|---|---|---|
| committer | Tristan Gingold <gingold@adacore.com> | 2009-11-09 13:50:30 +0000 |
| commit | 46b5151381235cc34bdbfab5bfdfd4d4b9d55d42 (patch) | |
| tree | c3aa505835b5c09ed987e7a2d1750e3e87ebd08e /sim/avr/interp.c | |
| parent | 3e4afc80cd4f4eaee8f791ef618f4acf6d587ee3 (diff) | |
| download | gdb-46b5151381235cc34bdbfab5bfdfd4d4b9d55d42.zip gdb-46b5151381235cc34bdbfab5bfdfd4d4b9d55d42.tar.gz gdb-46b5151381235cc34bdbfab5bfdfd4d4b9d55d42.tar.bz2 | |
2009-11-09 Tristan Gingold <gingold@adacore.com>
* avr/interp.c (sim_resume): Fix typo for OP_ret.
Diffstat (limited to 'sim/avr/interp.c')
| -rw-r--r-- | sim/avr/interp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/avr/interp.c b/sim/avr/interp.c index 8bb9ec2..903370f 100644 --- a/sim/avr/interp.c +++ b/sim/avr/interp.c @@ -985,7 +985,7 @@ sim_resume (SIM_DESC sd, int step, int signal) unsigned int sp = read_word (REG_SP); if (avr_pc22) { - pc = sram[++sp] = pc << 16; + pc = sram[++sp] << 16; cycles++; } else |