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| author | Jason Molenda <jmolenda@apple.com> | 1999-12-07 03:56:43 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 1999-12-07 03:56:43 +0000 |
| commit | c2d11a7da0372ef052af1c74d56e264d8aae4743 (patch) | |
| tree | b2ceadb275bb9a170315ab66111c1f643c9ebf71 /sim/arm | |
| parent | 1e37c28164d4f504b2ae8189d0b82a862cfa323d (diff) | |
| download | gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.zip gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.tar.gz gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.tar.bz2 | |
import gdb-1999-12-06 snapshot
Diffstat (limited to 'sim/arm')
| -rw-r--r-- | sim/arm/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/arm/armemu.c | 12 | ||||
| -rw-r--r-- | sim/arm/armos.c | 15 |
3 files changed, 26 insertions, 8 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index eb43255..bdaf8af 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,10 @@ +1999-11-22 Nick Clifton <nickc@cygnus.com> + + * armos.c (SWIread): Generate an error message if a huge read is + performed. + (SWIwrite): Generate an error message if a huge write is + performed. + 1999-10-27 Nick Clifton <nickc@cygnus.com> * thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index fa994e0..b9b669d 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -878,7 +878,6 @@ mainswitch: break ; case 0x10 : /* TST reg and MRS CPSR and SWP word */ - #ifdef MODET if (BITS(4,11) == 0xB) { /* STRH register offset, no write-back, down, pre indexed */ @@ -2410,13 +2409,13 @@ mainswitch: * Co-Processor Data Transfers * \***************************************************************************/ - case 0xc0 : - case 0xc4 : /* Store , No WriteBack , Post Dec */ + case 0xc4 : + case 0xc0 : /* Store , No WriteBack , Post Dec */ ARMul_STC(state,instr,LHS) ; break ; - case 0xc1 : - case 0xc5 : /* Load , No WriteBack , Post Dec */ + case 0xc5 : + case 0xc1 : /* Load , No WriteBack , Post Dec */ ARMul_LDC(state,instr,LHS) ; break ; @@ -2511,7 +2510,8 @@ mainswitch: * Co-Processor Register Transfers (MCR) and Data Ops * \***************************************************************************/ - case 0xe0 : case 0xe2 : case 0xe4 : case 0xe6 : + case 0xe2 : + case 0xe0 : case 0xe4 : case 0xe6 : case 0xe8 : case 0xea : case 0xec : case 0xee : if (BIT(4)) { /* MCR */ if (DESTReg == 15) { diff --git a/sim/arm/armos.c b/sim/arm/armos.c index 9f0f1fe..be4cbaf 100644 --- a/sim/arm/armos.c +++ b/sim/arm/armos.c @@ -308,6 +308,12 @@ SWIread (ARMul_State *state, ARMword f, ARMword ptr, ARMword len) int i; char *local = malloc (len); + if (local == NULL) + { + fprintf (stderr, "sim: Unable to read 0x%x bytes - out of memory\n", len); + return; + } + res = read (f, local, len); if (res > 0) for (i = 0; i < res; i++) @@ -325,10 +331,15 @@ SWIwrite (ARMul_State *state, ARMword f, ARMword ptr, ARMword len) int i; char *local = malloc (len); - for (i = 0; i < len; i++) + if (local == NULL) { - local[i] = ARMul_ReadByte (state, ptr + i); + fprintf (stderr, "sim: Unable to write 0x%x bytes - out of memory\n", len); + return; } + + for (i = 0; i < len; i++) + local[i] = ARMul_ReadByte (state, ptr + i); + res = write (f, local, len); state->Reg[0] = res == -1 ? -1 : len - res; free (local); |