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| author | Nick Clifton <nickc@redhat.com> | 2021-04-26 17:16:20 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2021-04-26 17:17:34 +0100 |
| commit | f6b9562fd912cc507ef4eb8be9ccb9f132810758 (patch) | |
| tree | fd1472bf93ba62ce4d74655c40c820747f27f63f /sim/arm | |
| parent | e8b6c1da565c93f015d93a4f8554830118e9bd07 (diff) | |
| download | gdb-f6b9562fd912cc507ef4eb8be9ccb9f132810758.zip gdb-f6b9562fd912cc507ef4eb8be9ccb9f132810758.tar.gz gdb-f6b9562fd912cc507ef4eb8be9ccb9f132810758.tar.bz2 | |
Fix a bug in the ARM emulator which would not allow 4 byte alignment for double word stores.
PR 22790
* armemu.c (Handle_Store_Double): Allow 4 byte alignment when
running in v6 mode.
Diffstat (limited to 'sim/arm')
| -rw-r--r-- | sim/arm/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/arm/armemu.c | 5 |
2 files changed, 10 insertions, 1 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index aa3c91b..fbd977c 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,9 @@ +2021-04-26 Nick Clifton <nickc@redhat.com> + + PR 22790 + * armemu.c (Handle_Store_Double): Allow 4 byte alignment when + running in v6 mode. + 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 922c2e4..f93ad0c 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -5457,7 +5457,10 @@ Handle_Store_Double (ARMul_State * state, ARMword instr) addr = base; /* The address must be aligned on a 8 byte boundary. */ - if (addr & 0x7) + if (state->is_v6 && (addr & 0x3) == 0) + /* Word alignment is enough for v6. */ + ; + else if (addr & 0x7) { #ifdef ABORTS ARMul_DATAABORT (addr); |