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authorDominik Vogt <vogt@linux.vnet.ibm.com>2015-12-15 14:09:14 +0100
committerAndreas Arnez <arnez@linux.vnet.ibm.com>2015-12-15 14:09:14 +0100
commit1d19cae752a7b032b8253feb4fa3b9f1dc162823 (patch)
treefcd5b5f015c8f9dc4e541049369e89e52ab6c8ba /sim/arm
parent08832196accd270fa053e8125c21e7a54ab19fe0 (diff)
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Fix invalid left shift of negative value
Fix occurrences of left-shifting negative constants in C code. sim/arm/ChangeLog: * thumbemu.c (handle_T2_insn): Fix left shift of negative value. * armemu.c (handle_v6_insn): Likewise. sim/avr/ChangeLog: * interp.c (sign_ext): Fix left shift of negative value. sim/mips/ChangeLog: * micromips.igen (process_isa_mode): Fix left shift of negative value. sim/msp430/ChangeLog: * msp430-sim.c (get_op, put_op): Fix left shift of negative value. sim/v850/ChangeLog: * simops.c (v850_bins): Fix left shift of negative value.
Diffstat (limited to 'sim/arm')
-rw-r--r--sim/arm/ChangeLog5
-rw-r--r--sim/arm/armemu.c40
-rw-r--r--sim/arm/thumbemu.c16
3 files changed, 33 insertions, 28 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index f87e18b..dec5dc5 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * thumbemu.c (handle_T2_insn): Fix left shift of negative value.
+ * armemu.c (handle_v6_insn): Likewise.
+
2015-11-14 Mike Frysinger <vapier@gentoo.org>
* wrapper.c (sim_close): Delete.
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index f2a84eb..3826c78 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -351,11 +351,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{
n = (val1 >> i) & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = (val2 >> i) & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n + m;
@@ -371,11 +371,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
n = val1 & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = (val2 >> 16) & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n - m;
@@ -388,11 +388,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
n = (val1 >> 16) & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = val2 & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n + m;
@@ -407,11 +407,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
n = val1 & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = (val2 >> 16) & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n + m;
@@ -424,11 +424,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
n = (val1 >> 16) & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = val2 & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n - m;
@@ -447,11 +447,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{
n = (val1 >> i) & 0xFFFF;
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -(1 << 16);
m = (val2 >> i) & 0xFFFF;
if (m & 0x8000)
- m |= -1 << 16;
+ m |= -(1 << 16);
r = n - m;
@@ -471,11 +471,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{
n = (val1 >> i) & 0xFF;
if (n & 0x80)
- n |= -1 << 8;
+ n |= - (1 << 8);
m = (val2 >> i) & 0xFF;
if (m & 0x80)
- m |= -1 << 8;
+ m |= - (1 << 8);
r = n + m;
@@ -495,11 +495,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{
n = (val1 >> i) & 0xFF;
if (n & 0x80)
- n |= -1 << 8;
+ n |= - (1 << 8);
m = (val2 >> i) & 0xFF;
if (m & 0x80)
- m |= -1 << 8;
+ m |= - (1 << 8);
r = n - m;
@@ -951,14 +951,14 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
state->Emulate = FALSE;
}
- mask = -1 << lsb;
- mask &= ~(-1 << (msb + 1));
+ mask = -(1 << lsb);
+ mask &= ~(-(1 << (msb + 1)));
state->Reg[Rd] &= ~ mask;
Rn = BITS (0, 3);
if (Rn != 0xF)
{
- ARMword val = state->Reg[Rn] & ~(-1 << ((msb + 1) - lsb));
+ ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
state->Reg[Rd] |= val << lsb;
}
return 1;
@@ -1036,7 +1036,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
val = state->Reg[Rn];
val >>= lsb;
- val &= ~(-1 << (widthm1 + 1));
+ val &= ~(-(1 << (widthm1 + 1)));
state->Reg[Rd] = val;
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 2d26bf6..72929c7 100644
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -204,7 +204,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
if (S)
- simm32 |= (-1 << 20);
+ simm32 |= -(1 << 20);
break;
}
@@ -217,7 +217,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
if (S)
- simm32 |= (-1 << 24);
+ simm32 |= -(1 << 24);
break;
}
@@ -230,7 +230,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10h << 12) | (imm10l << 2);
if (S)
- simm32 |= (-1 << 24);
+ simm32 |= -(1 << 24);
CLEART;
state->Reg[14] = (pc + 4) | 1;
@@ -246,7 +246,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
if (S)
- simm32 |= (-1 << 24);
+ simm32 |= -(1 << 24);
state->Reg[14] = (pc + 4) | 1;
break;
}
@@ -1078,7 +1078,7 @@ handle_T2_insn (ARMul_State * state,
ARMword Rn = tBITS (0, 3);
ARMword msbit = ntBITS (0, 5);
ARMword lsbit = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword mask = -1 << lsbit;
+ ARMword mask = -(1 << lsbit);
tASSERT (tBIT (4) == 0);
tASSERT (ntBIT (15) == 0);
@@ -1489,7 +1489,7 @@ handle_T2_insn (ARMul_State * state,
state->Reg[Rt] = ARMul_LoadByte (state, address);
if (state->Reg[Rt] & 0x80)
- state->Reg[Rt] |= -1 << 8;
+ state->Reg[Rt] |= -(1 << 8);
* pvalid = t_resolved;
break;
@@ -1542,7 +1542,7 @@ handle_T2_insn (ARMul_State * state,
state->Reg[Rt] = ARMul_LoadHalfWord (state, address);
if (state->Reg[Rt] & 0x8000)
- state->Reg[Rt] |= -1 << 16;
+ state->Reg[Rt] |= -(1 << 16);
* pvalid = t_branch;
break;
@@ -1564,7 +1564,7 @@ handle_T2_insn (ARMul_State * state,
val = state->Reg[Rm];
val = (val >> ror) | (val << (32 - ror));
if (val & 0x8000)
- val |= -1 << 16;
+ val |= -(1 << 16);
state->Reg[Rd] = val;
}
else