diff options
| author | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:19:29 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:19:29 +0000 |
| commit | cf52c765b09c13868d5cc5a8eb0297854be660d5 (patch) | |
| tree | 00d14d325741ffd2f05ff67a9360b6df05f9c583 /sim/arm | |
| parent | 4ef2594f4ed0fe4191d9e791e84b6241f968fc7c (diff) | |
| download | gdb-cf52c765b09c13868d5cc5a8eb0297854be660d5.zip gdb-cf52c765b09c13868d5cc5a8eb0297854be660d5.tar.gz gdb-cf52c765b09c13868d5cc5a8eb0297854be660d5.tar.bz2 | |
* armemu.h (GETSPSR): Call ARMul_GetSPSR().
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
Diffstat (limited to 'sim/arm')
| -rw-r--r-- | sim/arm/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/arm/armemu.h | 2 | ||||
| -rw-r--r-- | sim/arm/armsupp.c | 13 |
3 files changed, 18 insertions, 4 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index e401eef..1b3a557 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,5 +1,12 @@ 2000-07-04 Alexandre Oliva <aoliva@redhat.com> + * armemu.h (GETSPSR): Call ARMul_GetSPSR(). + * armsupp.c (ARMul_CPSRAltered): Zero out bits as they're + extracted from state->Cpsr, but preserve the unused bits. + (ARMul_GetCPSR): Get bits preserved in state->Cpsr. + (ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to + get the full CPSR word. + * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New. (SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros. (SETPSR, SET_INTMODE, SETCC): Removed. diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h index 5e832f2..da7fb2b 100644 --- a/sim/arm/armemu.h +++ b/sim/arm/armemu.h @@ -163,7 +163,7 @@ extern ARMword isize; #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC #endif -#define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ; +#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) diff --git a/sim/arm/armsupp.c b/sim/arm/armsupp.c index 6930529..27ee35b 100644 --- a/sim/arm/armsupp.c +++ b/sim/arm/armsupp.c @@ -183,7 +183,7 @@ ARMul_SetR15 (ARMul_State * state, ARMword value) ARMword ARMul_GetCPSR (ARMul_State * state) { - return (CPSR); + return (CPSR | state->Cpsr); } /***************************************************************************\ @@ -205,7 +205,7 @@ ARMul_SetCPSR (ARMul_State * state, ARMword value) void ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) { - state->Cpsr = CPSR; + state->Cpsr = ARMul_GetCPSR (state); if (state->Bank != USERBANK) { /* In user mode, only write flags */ if (BIT (16)) @@ -230,7 +230,7 @@ ARMul_GetSPSR (ARMul_State * state, ARMword mode) ARMword bank = ModeToBank (mode & MODEBITS); if (! BANK_CAN_ACCESS_SPSR (bank)) - return CPSR; + return ARMul_GetCPSR (state); return state->Spsr[bank]; } @@ -290,14 +290,21 @@ ARMul_CPSRAltered (ARMul_State * state) state->NtransSig = (state->Mode & 3) ? HIGH : LOW; } + state->Cpsr &= ~MODEBITS; ASSIGNINT (state->Cpsr & INTBITS); + state->Cpsr &= ~INTBITS; ASSIGNN ((state->Cpsr & NBIT) != 0); + state->Cpsr &= ~NBIT; ASSIGNZ ((state->Cpsr & ZBIT) != 0); + state->Cpsr &= ~ZBIT; ASSIGNC ((state->Cpsr & CBIT) != 0); + state->Cpsr &= ~CBIT; ASSIGNV ((state->Cpsr & VBIT) != 0); + state->Cpsr &= ~VBIT; #ifdef MODET ASSIGNT ((state->Cpsr & TBIT) != 0); + state->Cpsr &= ~TBIT; #endif if (oldmode > SVC26MODE) |