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authorMike Frysinger <vapier@gentoo.org>2015-03-30 02:41:51 -0400
committerMike Frysinger <vapier@gentoo.org>2015-03-30 12:58:23 -0400
commit58b991b14e7c2e26805cb8cf98e384dbd8afcd38 (patch)
tree5f47f233d3ed98a10615cc120269d971bb2afd8d /sim/arm
parentc4c9c44f57763ef4acacb440cdf601f5ce087edb (diff)
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sim: arm: clean up misc warnings
Also delete a few unused funcs.
Diffstat (limited to 'sim/arm')
-rw-r--r--sim/arm/ChangeLog19
-rw-r--r--sim/arm/armemu.c5
-rw-r--r--sim/arm/armemu.h51
-rw-r--r--sim/arm/armsupp.c5
-rw-r--r--sim/arm/bag.c6
-rw-r--r--sim/arm/maverick.c49
-rw-r--r--sim/arm/wrapper.c16
7 files changed, 54 insertions, 97 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 6ceed8b..0c685cc 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,5 +1,24 @@
2015-03-30 Mike Frysinger <vapier@gentoo.org>
+ * armemu.c [MODE32] (handle_v6_insn): Move definition.
+ (ARMul_Emulate26): Initialize do_int after label target.
+ * armemu.h (UNDEF_Test, UNDEF_Shift, UNDEF_MSRPC, UNDEF_MRSPC,
+ UNDEF_MULPCDest, UNDEF_MULDestEQOp1, UNDEF_LSRBPC,
+ UNDEF_LSRBaseEQOffWb, UNDEF_LSRBaseEQDestWb, UNDEF_LSRPCBaseWb,
+ UNDEF_LSRPCOffWb, UNDEF_LSMNoRegs, UNDEF_LSMPCBase,
+ UNDEF_LSMUserBankWb, UNDEF_LSMBaseInListWb, UNDEF_SWPPC,
+ UNDEF_CoProHS, UNDEF_MCRPC, UNDEF_LSCPCBaseWb,
+ UNDEF_UndefNotBounced, UNDEF_ShortInt, UNDEF_IllegalMode,
+ UNDEF_Prog32SigChange, UNDEF_Data32SigChange): Define to while(0).
+ * armsupp.c (ARMul_Align): Convert old style prototype.
+ * bag.c (addtolist, killwholelist): Mark static.
+ (BAG_newbag): Convert old style prototype.
+ * maverick.c (mv_compute_host_endianness): Delete.
+ * wrapper.c (verbosity, sim_set_verbose): Delete.
+ (init): Set state->verbose to 0.
+
+2015-03-30 Mike Frysinger <vapier@gentoo.org>
+
* configure.ac: Call SIM_AC_OPTION_ENDIAN, SIM_AC_OPTION_ALIGNMENT,
SIM_AC_OPTION_HOSTENDIAN, SIM_AC_OPTION_ENVIRONMENT,
SIM_AC_OPTION_INLINE, and SIM_AC_OPTION_WARNINGS.
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index d535a4e..07bfbb6 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -272,6 +272,7 @@ extern int stop_simulator;
/* Attempt to emulate an ARMv6 instruction.
Returns non-zero upon success. */
+#ifdef MODE32
static int
handle_v6_insn (ARMul_State * state, ARMword instr)
{
@@ -473,6 +474,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
printf ("Unhandled v6 insn: UNKNOWN: %08x\n", instr);
return 0;
}
+#endif
/* EMULATION of ARM6. */
@@ -817,10 +819,11 @@ ARMul_Emulate26 (ARMul_State * state)
else
{
ARMword cp14r1;
- int do_int = 0;
+ int do_int;
state->CP14R0_CCD = -1;
check_PMUintr:
+ do_int = 0;
cp14r0 |= ARMul_CP14_R0_FLAG2;
(void) state->CPWrite[14] (state, 0, cp14r0);
diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h
index 419f799..484cc85 100644
--- a/sim/arm/armemu.h
+++ b/sim/arm/armemu.h
@@ -462,31 +462,32 @@ typedef enum
}
tdstate;
-/* Macros to scrutinize instructions. */
-#define UNDEF_Test
-#define UNDEF_Shift
-#define UNDEF_MSRPC
-#define UNDEF_MRSPC
-#define UNDEF_MULPCDest
-#define UNDEF_MULDestEQOp1
-#define UNDEF_LSRBPC
-#define UNDEF_LSRBaseEQOffWb
-#define UNDEF_LSRBaseEQDestWb
-#define UNDEF_LSRPCBaseWb
-#define UNDEF_LSRPCOffWb
-#define UNDEF_LSMNoRegs
-#define UNDEF_LSMPCBase
-#define UNDEF_LSMUserBankWb
-#define UNDEF_LSMBaseInListWb
-#define UNDEF_SWPPC
-#define UNDEF_CoProHS
-#define UNDEF_MCRPC
-#define UNDEF_LSCPCBaseWb
-#define UNDEF_UndefNotBounced
-#define UNDEF_ShortInt
-#define UNDEF_IllegalMode
-#define UNDEF_Prog32SigChange
-#define UNDEF_Data32SigChange
+/* Macros to scrutinize instructions. The dummy do loop is to keep the compiler
+ happy when the statement is used in an otherwise empty else statement. */
+#define UNDEF_Test do { ; } while (0)
+#define UNDEF_Shift do { ; } while (0)
+#define UNDEF_MSRPC do { ; } while (0)
+#define UNDEF_MRSPC do { ; } while (0)
+#define UNDEF_MULPCDest do { ; } while (0)
+#define UNDEF_MULDestEQOp1 do { ; } while (0)
+#define UNDEF_LSRBPC do { ; } while (0)
+#define UNDEF_LSRBaseEQOffWb do { ; } while (0)
+#define UNDEF_LSRBaseEQDestWb do { ; } while (0)
+#define UNDEF_LSRPCBaseWb do { ; } while (0)
+#define UNDEF_LSRPCOffWb do { ; } while (0)
+#define UNDEF_LSMNoRegs do { ; } while (0)
+#define UNDEF_LSMPCBase do { ; } while (0)
+#define UNDEF_LSMUserBankWb do { ; } while (0)
+#define UNDEF_LSMBaseInListWb do { ; } while (0)
+#define UNDEF_SWPPC do { ; } while (0)
+#define UNDEF_CoProHS do { ; } while (0)
+#define UNDEF_MCRPC do { ; } while (0)
+#define UNDEF_LSCPCBaseWb do { ; } while (0)
+#define UNDEF_UndefNotBounced do { ; } while (0)
+#define UNDEF_ShortInt do { ; } while (0)
+#define UNDEF_IllegalMode do { ; } while (0)
+#define UNDEF_Prog32SigChange do { ; } while (0)
+#define UNDEF_Data32SigChange do { ; } while (0)
/* Prototypes for exported functions. */
extern unsigned ARMul_NthReg (ARMword, unsigned);
diff --git a/sim/arm/armsupp.c b/sim/arm/armsupp.c
index e2bac55..113f080 100644
--- a/sim/arm/armsupp.c
+++ b/sim/arm/armsupp.c
@@ -736,10 +736,7 @@ IntPending (ARMul_State * state)
/* Align a word access to a non word boundary. */
ARMword
-ARMul_Align (state, address, data)
- ARMul_State * state ATTRIBUTE_UNUSED;
- ARMword address;
- ARMword data;
+ARMul_Align (ARMul_State *state ATTRIBUTE_UNUSED, ARMword address, ARMword data)
{
/* This code assumes the address is really unaligned,
as a shift by 32 is undefined in C. */
diff --git a/sim/arm/bag.c b/sim/arm/bag.c
index 6cd8a95..35f2953 100644
--- a/sim/arm/bag.c
+++ b/sim/arm/bag.c
@@ -40,7 +40,7 @@ Hashentry;
Hashentry *lookupbyfirst[HASH_TABLE_SIZE];
Hashentry *lookupbysecond[HASH_TABLE_SIZE];
-void
+static void
addtolist (Hashentry ** add, long first, long second)
{
while (*add)
@@ -52,7 +52,7 @@ addtolist (Hashentry ** add, long first, long second)
(*add)->second = second;
}
-void
+static void
killwholelist (Hashentry * p)
{
Hashentry *q;
@@ -152,7 +152,7 @@ BAG_killpair_bysecond (long second)
}
void
-BAG_newbag ()
+BAG_newbag (void)
{
int i;
diff --git a/sim/arm/maverick.c b/sim/arm/maverick.c
index 8c9ff81..1b0dca9 100644
--- a/sim/arm/maverick.c
+++ b/sim/arm/maverick.c
@@ -1230,52 +1230,3 @@ mv_setReg64int (int regnum, long long val)
DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index];
DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index];
}
-
-/* Compute LSW in a double and a long long. */
-
-void
-mv_compute_host_endianness (ARMul_State * state)
-{
- static union
- {
- long long ll;
- long ints[2];
- long i;
- double d;
- float floats[2];
- float f;
- } conv;
-
- /* Calculate where's the LSW in a 64bit int. */
- conv.ll = 45;
-
- if (conv.ints[0] == 0)
- {
- msw_int_index = 0;
- lsw_int_index = 1;
- }
- else
- {
- assert (conv.ints[1] == 0);
- msw_int_index = 1;
- lsw_int_index = 0;
- }
-
- /* Calculate where's the LSW in a double. */
- conv.d = 3.0;
-
- if (conv.ints[0] == 0)
- {
- msw_float_index = 0;
- lsw_float_index = 1;
- }
- else
- {
- assert (conv.ints[1] == 0);
- msw_float_index = 1;
- lsw_float_index = 0;
- }
-
- printfdbg ("lsw_int_index %d\n", lsw_int_index);
- printfdbg ("lsw_float_index %d\n", lsw_float_index);
-}
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 0ccc7fb..c1b5321 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -52,9 +52,6 @@ static char *myname;
/* Memory size in bytes. */
static int mem_size = (1 << 21);
-/* Non-zero to display start up banner, and maybe other things. */
-static int verbosity;
-
/* Non-zero to set big endian mode. */
static int big_endian;
@@ -152,22 +149,11 @@ init (void)
state->bigendSig = (big_endian ? HIGH : LOW);
ARMul_MemoryInit (state, mem_size);
ARMul_OSInit (state);
- state->verbose = verbosity;
+ state->verbose = 0;
done = 1;
}
}
-/* Set verbosity level of simulator.
- This is not intended to produce detailed tracing or debugging information.
- Just summaries. */
-/* FIXME: common/run.c doesn't do this yet. */
-
-void
-sim_set_verbose (int v)
-{
- verbosity = v;
-}
-
/* Set the memory size to SIZE bytes.
Must be called before initializing simulator. */
/* FIXME: Rename to sim_set_mem_size. */