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| author | Nick Clifton <nickc@redhat.com> | 2015-06-28 19:14:36 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-06-28 19:14:36 +0100 |
| commit | 73cb0348b296656e971c4d428aa63781e656a1c4 (patch) | |
| tree | ddb71aae6c4ea1858ed6307f71451a72ff1c6919 /sim/arm/wrapper.c | |
| parent | ee0c0c503deffb7baf900ac8e092b18bf8c1528a (diff) | |
| download | gdb-73cb0348b296656e971c4d428aa63781e656a1c4.zip gdb-73cb0348b296656e971c4d428aa63781e656a1c4.tar.gz gdb-73cb0348b296656e971c4d428aa63781e656a1c4.tar.bz2 | |
Add support for ARM v6 instructions.
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
Diffstat (limited to 'sim/arm/wrapper.c')
| -rw-r--r-- | sim/arm/wrapper.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index d69daa3..b494354 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -257,6 +257,11 @@ sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED, mach = 0; } +#ifdef MODET + if (abfd != NULL && (bfd_get_start_address (abfd) & 1)) + SETT; +#endif + switch (mach) { default: @@ -341,17 +346,6 @@ sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED, break; } - if ( mach != bfd_mach_arm_3 - && mach != bfd_mach_arm_3M - && mach != bfd_mach_arm_2 - && mach != bfd_mach_arm_2a) - { - /* Reset mode to ARM. A gdb user may rerun a program that had entered - THUMB mode from the start and cause the ARM-mode startup code to be - executed in THUMB mode. */ - ARMul_SetCPSR (state, SVC32MODE); - } - memset (& info, 0, sizeof (info)); INIT_DISASSEMBLE_INFO (info, stdout, op_printf); info.read_memory_func = sim_dis_read; |