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| author | Stan Shebs <shebs@codesourcery.com> | 1999-04-16 01:35:26 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@codesourcery.com> | 1999-04-16 01:35:26 +0000 |
| commit | c906108c21474dfb4ed285bcc0ac6fe02cd400cc (patch) | |
| tree | a0015aa5cedc19ccbab307251353a41722a3ae13 /sim/arm/tconfig.in | |
| parent | cd946cff9ede3f30935803403f06f6ed30cad136 (diff) | |
| download | gdb-c906108c21474dfb4ed285bcc0ac6fe02cd400cc.zip gdb-c906108c21474dfb4ed285bcc0ac6fe02cd400cc.tar.gz gdb-c906108c21474dfb4ed285bcc0ac6fe02cd400cc.tar.bz2 | |
Initial creation of sourceware repositorygdb-4_18-branchpoint
Diffstat (limited to 'sim/arm/tconfig.in')
| -rw-r--r-- | sim/arm/tconfig.in | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sim/arm/tconfig.in b/sim/arm/tconfig.in new file mode 100644 index 0000000..04f702d --- /dev/null +++ b/sim/arm/tconfig.in @@ -0,0 +1,17 @@ +/* ARM target configuration file. */ + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +/* #define SIM_HAVE_PROFILE */ + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +/* #define SIM_HAVE_SIMCACHE */ + +/* Define this if the target cpu is bi-endian + and the simulator supports it. */ +#define SIM_HAVE_BIENDIAN |