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| author | Dominik Vogt <vogt@linux.vnet.ibm.com> | 2015-12-15 14:09:14 +0100 |
|---|---|---|
| committer | Andreas Arnez <arnez@linux.vnet.ibm.com> | 2015-12-15 14:09:14 +0100 |
| commit | 1d19cae752a7b032b8253feb4fa3b9f1dc162823 (patch) | |
| tree | fcd5b5f015c8f9dc4e541049369e89e52ab6c8ba /sim/arm/armemu.c | |
| parent | 08832196accd270fa053e8125c21e7a54ab19fe0 (diff) | |
| download | gdb-1d19cae752a7b032b8253feb4fa3b9f1dc162823.zip gdb-1d19cae752a7b032b8253feb4fa3b9f1dc162823.tar.gz gdb-1d19cae752a7b032b8253feb4fa3b9f1dc162823.tar.bz2 | |
Fix invalid left shift of negative value
Fix occurrences of left-shifting negative constants in C code.
sim/arm/ChangeLog:
* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
* armemu.c (handle_v6_insn): Likewise.
sim/avr/ChangeLog:
* interp.c (sign_ext): Fix left shift of negative value.
sim/mips/ChangeLog:
* micromips.igen (process_isa_mode): Fix left shift of negative
value.
sim/msp430/ChangeLog:
* msp430-sim.c (get_op, put_op): Fix left shift of negative value.
sim/v850/ChangeLog:
* simops.c (v850_bins): Fix left shift of negative value.
Diffstat (limited to 'sim/arm/armemu.c')
| -rw-r--r-- | sim/arm/armemu.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index f2a84eb..3826c78 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -351,11 +351,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) { n = (val1 >> i) & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = (val2 >> i) & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n + m; @@ -371,11 +371,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */ n = val1 & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = (val2 >> 16) & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n - m; @@ -388,11 +388,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) n = (val1 >> 16) & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = val2 & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n + m; @@ -407,11 +407,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */ n = val1 & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = (val2 >> 16) & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n + m; @@ -424,11 +424,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) n = (val1 >> 16) & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = val2 & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n - m; @@ -447,11 +447,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) { n = (val1 >> i) & 0xFFFF; if (n & 0x8000) - n |= -1 << 16; + n |= -(1 << 16); m = (val2 >> i) & 0xFFFF; if (m & 0x8000) - m |= -1 << 16; + m |= -(1 << 16); r = n - m; @@ -471,11 +471,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) { n = (val1 >> i) & 0xFF; if (n & 0x80) - n |= -1 << 8; + n |= - (1 << 8); m = (val2 >> i) & 0xFF; if (m & 0x80) - m |= -1 << 8; + m |= - (1 << 8); r = n + m; @@ -495,11 +495,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr) { n = (val1 >> i) & 0xFF; if (n & 0x80) - n |= -1 << 8; + n |= - (1 << 8); m = (val2 >> i) & 0xFF; if (m & 0x80) - m |= -1 << 8; + m |= - (1 << 8); r = n - m; @@ -951,14 +951,14 @@ handle_v6_insn (ARMul_State * state, ARMword instr) state->Emulate = FALSE; } - mask = -1 << lsb; - mask &= ~(-1 << (msb + 1)); + mask = -(1 << lsb); + mask &= ~(-(1 << (msb + 1))); state->Reg[Rd] &= ~ mask; Rn = BITS (0, 3); if (Rn != 0xF) { - ARMword val = state->Reg[Rn] & ~(-1 << ((msb + 1) - lsb)); + ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb))); state->Reg[Rd] |= val << lsb; } return 1; @@ -1036,7 +1036,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr) val = state->Reg[Rn]; val >>= lsb; - val &= ~(-1 << (widthm1 + 1)); + val &= ~(-(1 << (widthm1 + 1))); state->Reg[Rd] = val; |