Add support for instruction level tracing to the ARM simulator.

	* wrapper.c (op_print): New function.
	(sim_dis_read): New function.
	(print_insn): New function - disassembles the given instruction.
	(sim_trace): Note that tracing is now allowed.
	(sim_create_inferior): Default to emulating v6.
	Initialise the disassembler machinery.
	(sim_target_parse_command_line): Add support for -t -d and -z
	options.
	(sim_target_display_usage): Note existence of -d and -z options.
	(sim_open): Parse -t -d and -z options.
	* armemu.h: Add exports of trace, disas and trace_funcs.
	Add prototype for print_insn.
	* armemu.c (ARMul_Emulate26): Add tracing code.
	Delete unused variables.
	* thumbemu (handle_v6_thumb_insn): Delete unused variable Rd.
	Move Rm variable into switch cases.
	Add tracing code.

	* armcopro.c (XScale_cp15_init): Add a return value.
	(XScale_cp13_init): Likewise.
	(XScale_cp14_init): Likewise.
	(XScale_cp15_LDC): Delete unused function.
	(XScale_cp15_STC): Likewise.
	* maverick.c: Delete comment inside comment.
	(DSPInit): Delete unused function.
	(DSPMCR4): Fix compile time warning about missing parenthesis.
	(DSPMCR5): Likewise.
	(DSPCDP6): Delete unused variable opcode2.

1 files changed, 38 insertions, 15 deletions

diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 64c0146..d535a4e 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1,7 +1,7 @@
 /*  armemu.c -- Main instruction emulation:  ARM7 Instruction Emulator.
     Copyright (C) 1994 Advanced RISC Machines Ltd.
     Modifications to add arch. v4 support by <jsmith@cygnus.com>.
-    
+
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
     the Free Software Foundation; either version 3 of the License, or
@@ -314,7 +314,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
       {
 	ARMword Rm;
 	int ror = -1;
-	  
+
 	switch (BITS (4, 11))
 	  {
 	  case 0x07: ror = 0; break;
@@ -580,11 +580,20 @@ ARMul_Emulate26 (ARMul_State * state)
 
       if (state->EventSet)
 	ARMul_EnvokeEvent (state);
-#if 0 /* Enable this for a helpful bit of debugging when tracing is needed.  */
-      fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
-      if (instr == 0)
-	abort ();
-#endif
+
+      if (! TFLAG && trace)
+	{
+	  fprintf (stderr, "pc: %x, ", pc & ~1);
+	  if (! disas)
+	    fprintf (stderr, "instr: %x\n", instr);
+	}
+
+      if (instr == 0 || pc < 0x10)
+	{
+	  ARMul_Abort (state, ARMUndefinedInstrV);
+	  state->Emulate = FALSE;
+	}
+
 #if 0 /* Enable this code to help track down stack alignment bugs.  */
       {
 	static ARMword old_sp = -1;
@@ -628,8 +637,8 @@ ARMul_Emulate26 (ARMul_State * state)
 	    }
 	  if (state->Debug)
 	    {
-	      fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n", pc, instr,
-		       state->Mode);
+	      fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n",
+		       (long) pc, (long) instr, (long) state->Mode);
 	      (void) fgetc (stdin);
 	    }
 	}
@@ -667,6 +676,14 @@ ARMul_Emulate26 (ARMul_State * state)
 
 	    case t_decoded:
 	      /* ARM instruction available.  */
+	      if (disas || trace)
+		{
+		  fprintf (stderr, "  emulate as: ");
+		  if (trace)
+		    fprintf (stderr, "%08x ", new);
+		  if (! disas)
+		    fprintf (stderr, "\n");
+		}
 	      instr = new;
 	      /* So continue instruction decoding.  */
 	      break;
@@ -675,6 +692,8 @@ ARMul_Emulate26 (ARMul_State * state)
 	    }
 	}
 #endif
+      if (disas)
+	print_insn (instr);
 
       /* Check the condition codes.  */
       if ((temp = TOPBITS (28)) == AL)
@@ -1654,7 +1673,6 @@ check_PMUintr:
 		{
 		  if (BITS (4, 7) == 0x7)
 		    {
-		      ARMword value;
 		      extern int SWI_vector_installed;
 
 		      /* Hardware is allowed to optionally override this
@@ -1736,7 +1754,6 @@ check_PMUintr:
 		      ARMdword op1 = state->Reg[BITS (0, 3)];
 		      ARMdword op2 = state->Reg[BITS (8, 11)];
 		      ARMdword dest;
-		      ARMdword result;
 
 		      if (BIT (5))
 			op1 >>= 16;
@@ -1877,7 +1894,6 @@ check_PMUintr:
 		      /* ElSegundo SMULxy insn.  */
 		      ARMword op1 = state->Reg[BITS (0, 3)];
 		      ARMword op2 = state->Reg[BITS (8, 11)];
-		      ARMword Rn = state->Reg[BITS (12, 15)];
 
 		      if (BIT (5))
 			op1 >>= 16;
@@ -3459,7 +3475,6 @@ check_PMUintr:
 	      FLUSHPIPE;
 	      break;
 
-
 	      /* Branch and Link forward.  */
 	    case 0xb0:
 	    case 0xb1:
@@ -3477,9 +3492,10 @@ check_PMUintr:
 #endif
 	      state->Reg[15] = pc + 8 + POSBRANCH;
 	      FLUSHPIPE;
+	      if (trace_funcs)
+		fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
 	      break;
 
-
 	      /* Branch and Link backward.  */
 	    case 0xb8:
 	    case 0xb9:
@@ -3497,9 +3513,10 @@ check_PMUintr:
 #endif
 	      state->Reg[15] = pc + 8 + NEGBRANCH;
 	      FLUSHPIPE;
+	      if (trace_funcs)
+		fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
 	      break;
 
-
 	      /* Co-Processor Data Transfers.  */
 	    case 0xc4:
 	      if (state->is_v5)
@@ -4150,6 +4167,8 @@ WriteR15 (ARMul_State * state, ARMword src)
 #endif
 
   FLUSHPIPE;
+  if (trace_funcs)
+    fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
 }
 
 /* This routine handles writes to register 15 when the S bit is set.  */
@@ -4187,6 +4206,8 @@ WriteSR15 (ARMul_State * state, ARMword src)
   ARMul_R15Altered (state);
 #endif
   FLUSHPIPE;
+  if (trace_funcs)
+    fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
 }
 
 /* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
@@ -4208,6 +4229,8 @@ WriteR15Branch (ARMul_State * state, ARMword src)
       state->Reg[15] = src & 0xfffffffc;
     }
   FLUSHPIPE;
+  if (trace_funcs)
+    fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
 #else
   WriteR15 (state, src);
 #endif