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authorNick Clifton <nickc@redhat.com>2000-08-15 00:10:52 +0000
committerNick Clifton <nickc@redhat.com>2000-08-15 00:10:52 +0000
commit4bc1de7b2d5e2003fd54d4e7443b44d424cefe96 (patch)
tree8d8d0ce9074e6ac0c6b406004a5634959577efc6 /sim/arm/armemu.c
parent046b3b54ee25c1e6d3af4fc24d70778d413a2877 (diff)
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Compute write back value for post increment loads before
performing the load in case the offset register is overwritten.
Diffstat (limited to 'sim/arm/armemu.c')
-rw-r--r--sim/arm/armemu.c75
1 files changed, 41 insertions, 34 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 7152023..9d3dcba 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -106,60 +106,67 @@ extern int stop_simulator;
if (StoreHalfWord(state, instr, temp)) \
LSBase = temp ;
-/* load post decrement writeback */
+/* Load post decrement writeback. */
#define LHPOSTDOWN() \
{ \
- int done = 1 ; \
- lhs = LHS ; \
- switch (BITS(5,6)) { \
+ int done = 1; \
+ lhs = LHS; \
+ temp = lhs - GetLS7RHS (state, instr); \
+ \
+ switch (BITS (5, 6)) \
+ { \
case 1: /* H */ \
- if (LoadHalfWord(state,instr,lhs,LUNSIGNED)) \
- LSBase = lhs - GetLS7RHS(state,instr) ; \
- break ; \
+ if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
+ LSBase = temp; \
+ break; \
case 2: /* SB */ \
- if (LoadByte(state,instr,lhs,LSIGNED)) \
- LSBase = lhs - GetLS7RHS(state,instr) ; \
- break ; \
+ if (LoadByte (state, instr, lhs, LSIGNED)) \
+ LSBase = temp; \
+ break; \
case 3: /* SH */ \
- if (LoadHalfWord(state,instr,lhs,LSIGNED)) \
- LSBase = lhs - GetLS7RHS(state,instr) ; \
- break ; \
- case 0: /* SWP handled elsewhere */ \
+ if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
+ LSBase = temp; \
+ break; \
+ case 0: /* SWP handled elsewhere. */ \
default: \
- done = 0 ; \
- break ; \
+ done = 0; \
+ break; \
} \
if (done) \
- break ; \
+ break; \
}
-/* load post increment writeback */
+/* Load post increment writeback. */
#define LHPOSTUP() \
{ \
- int done = 1 ; \
- lhs = LHS ; \
- switch (BITS(5,6)) { \
+ int done = 1; \
+ lhs = LHS; \
+ temp = lhs + GetLS7RHS (state, instr); \
+ \
+ switch (BITS (5, 6)) \
+ { \
case 1: /* H */ \
- if (LoadHalfWord(state,instr,lhs,LUNSIGNED)) \
- LSBase = lhs + GetLS7RHS(state,instr) ; \
- break ; \
+ if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
+ LSBase = temp; \
+ break; \
case 2: /* SB */ \
- if (LoadByte(state,instr,lhs,LSIGNED)) \
- LSBase = lhs + GetLS7RHS(state,instr) ; \
- break ; \
+ if (LoadByte (state, instr, lhs, LSIGNED)) \
+ LSBase = temp; \
+ break; \
case 3: /* SH */ \
- if (LoadHalfWord(state,instr,lhs,LSIGNED)) \
- LSBase = lhs + GetLS7RHS(state,instr) ; \
- break ; \
- case 0: /* SWP handled elsewhere */ \
+ if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
+ LSBase = temp; \
+ break; \
+ case 0: /* SWP handled elsewhere. */ \
default: \
- done = 0 ; \
- break ; \
+ done = 0; \
+ break; \
} \
if (done) \
- break ; \
+ break; \
}
+
/* load pre decrement */
#define LHPREDOWN() \
{ \