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| author | Jason Molenda <jmolenda@apple.com> | 1999-07-12 11:15:22 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 1999-07-12 11:15:22 +0000 |
| commit | 43e526b9b4c9868d3cd90772a54f767f8d45cadd (patch) | |
| tree | 4d68a4a2d3a6c7e4f6237bc04015fc182a8ced0c /sim/arm/armemu.c | |
| parent | edac9bffc154855d959fcbc32e2fe0b073a9ec71 (diff) | |
| download | gdb-43e526b9b4c9868d3cd90772a54f767f8d45cadd.zip gdb-43e526b9b4c9868d3cd90772a54f767f8d45cadd.tar.gz gdb-43e526b9b4c9868d3cd90772a54f767f8d45cadd.tar.bz2 | |
import gdb-1999-07-12 snapshot
Diffstat (limited to 'sim/arm/armemu.c')
| -rw-r--r-- | sim/arm/armemu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 36b7bba..fa994e0 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -464,6 +464,7 @@ ARMword ARMul_Emulate26(register ARMul_State *state) if (temp) { /* if the condition codes don't match, stop here */ mainswitch: + switch ((int)BITS(20,27)) { /***************************************************************************\ @@ -877,6 +878,7 @@ mainswitch: break ; case 0x10 : /* TST reg and MRS CPSR and SWP word */ + #ifdef MODET if (BITS(4,11) == 0xB) { /* STRH register offset, no write-back, down, pre indexed */ |