diff options
author | Nick Clifton <nickc@redhat.com> | 2002-05-27 14:12:00 +0000 |
---|---|---|
committer | Nick Clifton <nickc@redhat.com> | 2002-05-27 14:12:00 +0000 |
commit | 10b57fcbd720b5fab5b54901e7c80a2b39898cc4 (patch) | |
tree | 24dd8123d4584f1b4d3de8d09e2b47b0cb85fa7b /sim/arm/armcopro.c | |
parent | f08caad151ffb2884eeb58c956f931ea8d30e0bf (diff) | |
download | gdb-10b57fcbd720b5fab5b54901e7c80a2b39898cc4.zip gdb-10b57fcbd720b5fab5b54901e7c80a2b39898cc4.tar.gz gdb-10b57fcbd720b5fab5b54901e7c80a2b39898cc4.tar.bz2 |
Only perform access checks if 'check' is set.
Report unknown machine numbers.
Formatting tidy ups.
Diffstat (limited to 'sim/arm/armcopro.c')
-rw-r--r-- | sim/arm/armcopro.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c index da409f0..8b04186 100644 --- a/sim/arm/armcopro.c +++ b/sim/arm/armcopro.c @@ -85,7 +85,6 @@ XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED) /* Initialise the ARM Control Register. */ XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078; - } /* Check an access to a register. */ @@ -253,7 +252,7 @@ write_cp15_reg (ARMul_State * state, value &= 0x00003b87; value |= 0x00000078; - /* Change the endianness if necessary */ + /* Change the endianness if necessary. */ if ((value & ARMul_CP15_R1_ENDIAN) != (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN)) { @@ -475,11 +474,11 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store) /* Check for PID-ification. XXX BTB access support will require this test failing. */ r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000); - if (r0 && (*address & 0xfe000000) == 0) - *address |= r0; + if (r0 && (* address & 0xfe000000) == 0) + * address |= r0; /* Check alignment fault enable/disable. */ - if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (*address & 3)) + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3)) ARMul_Abort (state, ARMul_DataAbortV); if (XScale_debug_moe (state, -1)) @@ -495,7 +494,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store) { /* r1 is a inverse mask. */ if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) - && ((*address & ~r1) == (r0 & ~r1))) + && ((* address & ~r1) == (r0 & ~r1))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); @@ -504,7 +503,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store) else { if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) - && ((*address & ~3) == (r0 & ~3))) + && ((* address & ~3) == (r0 & ~3))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); @@ -512,7 +511,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store) e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2; if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1)) - && ((*address & ~3) == (r1 & ~3))) + && ((* address & ~3) == (r1 & ~3))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); @@ -520,7 +519,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store) } } -/* Check set. */ +/* Set the XScale FSR and FAR registers. */ void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far) @@ -847,7 +846,7 @@ write_cp14_reg (unsigned reg, ARMword value) /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */ value &= 0x0ffff77f; - /* Reset the clock counter if necessary */ + /* Reset the clock counter if necessary. */ if (value & ARMul_CP14_R0_CLKRST) XScale_cp14_Regs [1] = 0; break; |