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author | Nick Clifton <nickc@redhat.com> | 2001-02-28 01:04:24 +0000 |
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committer | Nick Clifton <nickc@redhat.com> | 2001-02-28 01:04:24 +0000 |
commit | 917bca4f210f0b654abbb8497dd4f8abe5bf9e9f (patch) | |
tree | 578acea531543f8b6b6361923e6d8dba5b112955 /sim/arm/armcopro.c | |
parent | 3078eca93142e636b211897744a97b66569593b9 (diff) | |
download | gdb-917bca4f210f0b654abbb8497dd4f8abe5bf9e9f.zip gdb-917bca4f210f0b654abbb8497dd4f8abe5bf9e9f.tar.gz gdb-917bca4f210f0b654abbb8497dd4f8abe5bf9e9f.tar.bz2 |
Add support for disabling alignment checks when performing GDB interface
calls or SWI emulaiton routines. (Alignment checking code has not yet been
contributed).
Diffstat (limited to 'sim/arm/armcopro.c')
-rw-r--r-- | sim/arm/armcopro.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c index db7ee60..8605dcf 100644 --- a/sim/arm/armcopro.c +++ b/sim/arm/armcopro.c @@ -16,6 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "armdefs.h" +#include "armos.h" #include "armemu.h" #include "ansidecl.h" @@ -211,7 +212,7 @@ check_cp15_access (ARMul_State * state, /* Store a value into one of coprocessor 15's registers. */ void -write_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value) +write_cp15_reg (ARMul_State * state, unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value) { if (opcode_2) { @@ -324,9 +325,9 @@ write_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value) return; } -/* Return the value in a cp13 register. */ +/* Return the value in a cp15 register. */ -static ARMword +ARMword read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm) { if (opcode_2 == 0) @@ -364,7 +365,7 @@ XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data result = check_cp15_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) - write_cp15_reg (reg, 0, 0, data); + write_cp15_reg (state, reg, 0, 0, data); return result; } @@ -416,7 +417,7 @@ XScale_cp15_MCR (ARMul_State * state, result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2); if (result == ARMul_DONE) - write_cp15_reg (reg, opcode_2, CRm, value); + write_cp15_reg (state, reg, opcode_2, CRm, value); return result; } @@ -440,7 +441,7 @@ XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, { /* FIXME: Not sure what to do about the alternative register set here. For now default to just accessing CRm == 0 registers. */ - write_cp15_reg (reg, 0, 0, value); + write_cp15_reg (state, reg, 0, 0, value); return TRUE; } |