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authorNick Clifton <nickc@redhat.com>2000-11-30 01:55:12 +0000
committerNick Clifton <nickc@redhat.com>2000-11-30 01:55:12 +0000
commitf1129fb8ff9938330168992fb23ed35e37d82d61 (patch)
treeacb0e04459f40941f698cb91b1382354c885bb72 /sim/arm/ChangeLog
parent2a1aa0e97cefed26213a2b124e91e8d74d11a5d6 (diff)
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Add support for ARM's v5TE architecture and Intel's XScale extenstions
Diffstat (limited to 'sim/arm/ChangeLog')
-rw-r--r--sim/arm/ChangeLog28
1 files changed, 27 insertions, 1 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index b66a340..2c893e0 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,30 @@
+2000-11-29 Nick Clifton <nickc@redhat.com>
+
+ * armdefs.h (State): Add 'v5e' and 'xscale' fields.
+ (ARM_v5e_Prop): Define.
+ (ARM_XScale_Prop): Define.
+
+ * wrapper.c (sim_create_inferior): Select processor based on
+ machine number.
+ (SWI_vector_installed): New boolean. Set to true if the SWI
+ vector address is written to by the executable.
+
+ * arminit.c (ARMul_NewState): Switch default to 32 bit mode.
+ (ARMul_SelectProcessor): Initialise v5e and xscale signals.
+ (ARMul_Abort): Fix calculation of LR address.
+
+ * armos.c (ARMul_OSHandleSWI): If a SWI vector has been installed
+ and a SWI is not handled by the simulator, pass the SWI off to the
+ vector, otherwise issue a warning message and continue.
+
+ * armsupp.c (ARMul_CPSRAltered): Set S bit aswell.
+
+ * thumbemu.c: Add v5 instruction simulation.
+ * armemu.c: Add v5, XScale and El Segundo instruction simulation.
+
+ * armcopro.c: Add XScale co-processor emulation.
+ * armemu.h: Add exported XScale co-processor functions.
+
2000-09-15 Nick Clifton <nickc@redhat.com>
* armdefs.h: Rename StrongARM property to v4_ARM and add v5 ARM
@@ -189,7 +216,6 @@ Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
-
1999-05-08 Felix Lee <flee@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.