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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-04-08 12:06:31 -0700 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-04-08 12:08:20 -0700 |
| commit | b630840c9c22a877b2c6270880a214f7b451f546 (patch) | |
| tree | b3382832c450a81d5a25dd52703e7db7c3863411 /sim/aarch64 | |
| parent | ae27d3fe76ffb54e7d413a67d8c8d76ca78a9681 (diff) | |
| download | gdb-b630840c9c22a877b2c6270880a214f7b451f546.zip gdb-b630840c9c22a877b2c6270880a214f7b451f546.tar.gz gdb-b630840c9c22a877b2c6270880a214f7b451f546.tar.bz2 | |
Add support for fcvtl and fcvtl2.
sim/aarch64/
* simulator.c (do_vec_FCVTL): New.
(do_vec_op1): Call do_vec_FCVTL.
sim/testsuite/sim/aarch64/
* fcvtl.s: New.
Diffstat (limited to 'sim/aarch64')
| -rw-r--r-- | sim/aarch64/ChangeLog | 3 | ||||
| -rw-r--r-- | sim/aarch64/simulator.c | 48 |
2 files changed, 51 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 0b3d21d..42379df 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,5 +1,8 @@ 2017-04-08 Jim Wilson <jim.wilson@linaro.org> + * simulator.c (do_vec_FCVTL): New. + (do_vec_op1): Call do_vec_FCVTL. + * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New. (do_scalar_vec): Add calls to new functions. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index c2e02b1..16d8d8d 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -5468,6 +5468,47 @@ do_vec_ADDP (sim_cpu *cpu) } } +/* Float point vector convert to longer (precision). */ +static void +do_vec_FCVTL (sim_cpu *cpu) +{ + /* instr[31] = 0 + instr[30] = half (0) / all (1) + instr[29,23] = 00 1110 0 + instr[22] = single (0) / double (1) + instr[21,10] = 10 0001 0111 10 + instr[9,5] = Rn + instr[4,0] = Rd. */ + + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + unsigned full = INSTR (30, 30); + unsigned i; + + NYI_assert (31, 31, 0); + NYI_assert (29, 23, 0x1C); + NYI_assert (21, 10, 0x85E); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (INSTR (22, 22)) + { + for (i = 0; i < 2; i++) + aarch64_set_vec_double (cpu, rd, i, + aarch64_get_vec_float (cpu, rn, i + 2*full)); + } + else + { + HALT_NYI; + +#if 0 + /* TODO: Implement missing half-float support. */ + for (i = 0; i < 4; i++) + aarch64_set_vec_float (cpu, rd, i, + aarch64_get_vec_halffloat (cpu, rn, i + 4*full)); +#endif + } +} + static void do_vec_FABS (sim_cpu *cpu) { @@ -5717,6 +5758,13 @@ do_vec_op1 (sim_cpu *cpu) case 0x33: do_vec_FMLA (cpu); return; case 0x35: do_vec_fadd (cpu); return; + case 0x1E: + switch (INSTR (20, 16)) + { + case 0x01: do_vec_FCVTL (cpu); return; + default: HALT_NYI; + } + case 0x2E: switch (INSTR (20, 16)) { |