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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-03-03 13:10:45 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-03-03 13:10:45 -0800 |
| commit | 8ecbe595e69a84a0e3053884832d63af37113680 (patch) | |
| tree | ce6ff5924c03fd1d2287b713bb8150aaeccc4def /sim/aarch64/ChangeLog | |
| parent | df97be551faa262732128493c8ac159ae4b7f6d3 (diff) | |
| download | gdb-8ecbe595e69a84a0e3053884832d63af37113680.zip gdb-8ecbe595e69a84a0e3053884832d63af37113680.tar.gz gdb-8ecbe595e69a84a0e3053884832d63af37113680.tar.bz2 | |
Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.
sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
Diffstat (limited to 'sim/aarch64/ChangeLog')
| -rw-r--r-- | sim/aarch64/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index b6c0256..0bf305a 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2017-03-03 Jim Wilson <jim.wilson@linaro.org> + + * simulator.c (mul64hi): Shift carry left by 32. + (smulh): Change signum to negate. If negate, invert result, and add + carry bit if low part of multiply result is zero. + 2017-02-25 Jim Wilson <jim.wilson@linaro.org> * simulator.c (do_vec_SMOV_into_scalar): New. |