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| author | Tristan Gingold <gingold@adacore.com> | 2009-11-12 15:24:04 +0000 |
|---|---|---|
| committer | Tristan Gingold <gingold@adacore.com> | 2009-11-12 15:24:04 +0000 |
| commit | 8f0ac700824d511485f1b5608d789afa1c64fdb7 (patch) | |
| tree | 18dcd764d33ad0aeecda5772c70e846dbfb50976 /sim/ChangeLog | |
| parent | 33bcfade88c909dad35b582bd8b0e6f9f5d1e395 (diff) | |
| download | gdb-8f0ac700824d511485f1b5608d789afa1c64fdb7.zip gdb-8f0ac700824d511485f1b5608d789afa1c64fdb7.tar.gz gdb-8f0ac700824d511485f1b5608d789afa1c64fdb7.tar.bz2 | |
2009-11-12 Tristan Gingold <gingold@adacore.com>
* avr/interp.c (sim_write): Allow byte access.
(sim_read): Ditto.
Diffstat (limited to 'sim/ChangeLog')
| -rw-r--r-- | sim/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index 18f555c..35055a9 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,5 +1,10 @@ 2009-11-12 Tristan Gingold <gingold@adacore.com> + * avr/interp.c (sim_write): Allow byte access. + (sim_read): Ditto. + +2009-11-12 Tristan Gingold <gingold@adacore.com> + * avr/interp.c (sim_load): Clear memory before loading. 2009-11-09 Tristan Gingold <gingold@adacore.com> |