aboutsummaryrefslogtreecommitdiff
path: root/readline/histfile.c
diff options
context:
space:
mode:
authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>2019-08-12 17:17:18 +0100
committerNick Clifton <nickc@redhat.com>2019-08-12 17:17:18 +0100
commit08132bdd876fa1825810f90ecc25390dd4ded457 (patch)
tree2a803c56103c18a109093c5be9176efb05eee657 /readline/histfile.c
parent5312fe52e9ae6fd108f161a271315eb2821246eb (diff)
downloadgdb-08132bdd876fa1825810f90ecc25390dd4ded457.zip
gdb-08132bdd876fa1825810f90ecc25390dd4ded457.tar.gz
gdb-08132bdd876fa1825810f90ecc25390dd4ded457.tar.bz2
Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.
This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
Diffstat (limited to 'readline/histfile.c')
0 files changed, 0 insertions, 0 deletions