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| author | Nick Clifton <nickc@redhat.com> | 1999-10-25 15:28:44 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 1999-10-25 15:28:44 +0000 |
| commit | 9cac79d30bd2c66a3f91cd5803aadb9dc36bc24b (patch) | |
| tree | 10d1dfa4e27c463a317339810189e9348c5eff6f /opcodes | |
| parent | f084181a5b087d5f0ff050224154749ee916b05d (diff) | |
| download | gdb-9cac79d30bd2c66a3f91cd5803aadb9dc36bc24b.zip gdb-9cac79d30bd2c66a3f91cd5803aadb9dc36bc24b.tar.gz gdb-9cac79d30bd2c66a3f91cd5803aadb9dc36bc24b.tar.bz2 | |
Apply patch supplied for case 102229 to implement new insns psrclr and psrset.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/mcore-dis.c | 58 | ||||
| -rw-r--r-- | opcodes/mcore-opc.h | 4 |
3 files changed, 69 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c4f4045..9160f9e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +1999-10-25 Nick Clifton <nickc@cygnus.com> + + * mcore-opc.h (enum mcore_opclass): Add class OPSR. + (mcore_table): Add psrclr and psrset instructions. + + * mcore-dis.c (array imsk): Add mask for OPSR class. + (print_insn_mcore): Add decode for OPSR class insns. + 1999-10-18 Michael Meissner <meissner@cygnus.com> * alpha-opc.c (alpha_operands): Fill in missing initializer. diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c index 793de68..2c9f041 100644 --- a/opcodes/mcore-dis.c +++ b/opcodes/mcore-dis.c @@ -57,6 +57,52 @@ static const unsigned short imsk[] = /* OMc */ 0xFF00, /* SIa */ 0xFE00, +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <stdio.h> +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "mcore-opc.h" +#include "dis-asm.h" + +/* Mask for each mcore_opclass: */ +static const unsigned short imsk[] = +{ + /* O0 */ 0xFFFF, + /* OT */ 0xFFFC, + /* O1 */ 0xFFF0, + /* OC */ 0xFFE0, + /* O2 */ 0xFF00, + /* X1 */ 0xFFF0, + /* OI */ 0xFE00, + /* OB */ 0xFE00, + + /* OMa */ 0xFFF0, + /* SI */ 0xFE00, + /* I7 */ 0xF800, + /* LS */ 0xF000, + /* BR */ 0xF800, + /* BL */ 0xFF00, + /* LR */ 0xF000, + /* LJ */ 0xFF00, + + /* RM */ 0xFFF0, + /* RQ */ 0xFFF0, + /* JSR */ 0xFFF0, + /* JMP */ 0xFFF0, + /* OBRa*/ 0xFFF0, + /* OBRb*/ 0xFF80, + /* OBRc*/ 0xFF00, + /* OBR2*/ 0xFE00, + + /* O1R1*/ 0xFFF0, + /* OMb */ 0xFF80, + /* OMc */ 0xFF00, + /* SIa */ 0xFE00, + + /* OPSR */ 0xFFF8, /* psrset/psrclr */ + /* JC */ 0, /* JC,JU,JL don't appear in object */ /* JU */ 0, /* JL */ 0, @@ -237,6 +283,18 @@ print_insn_mcore (memaddr, info) } break; + case OPSR: + { + static char * fields[] = + { + "af", "ie", "fe", "fe,ie", + "ee", "ee,ie", "ee,fe", "ee,fe,ie" + }; + + fprintf (stream, "\t%s", fields[inst & 0x7]); + } + break; + default: /* if the disassembler lags the instruction set */ fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h index 606ba84..208b881 100644 --- a/opcodes/mcore-opc.h +++ b/opcodes/mcore-opc.h @@ -23,7 +23,7 @@ typedef enum O0, OT, O1, OC, O2, X1, OI, OB, OMa, SI, I7, LS, BR, BL, LR, LJ, RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2, - O1R1, OMb, OMc, SIa, + O1R1, OMb, OMc, SIa, OPSR, JC, JU, JL, RSI, DO21, OB2 } mcore_opclass; @@ -99,6 +99,8 @@ mcore_opcode_info mcore_table[] = { "tst", O2, 0, 0x0E00 }, { "cmpne", O2, 0, 0x0F00 }, { "mfcr", OC, 0, 0x1000 }, + { "psrclr", OPSR, 0, 0x11F0 }, + { "psrset", OPSR, 0, 0x11F8 }, { "mov", O2, 0, 0x1200 }, { "bgenr", O2, 0, 0x1300 }, { "rsub", O2, 0, 0x1400 }, |