* mn10300-opc.c (mn10300_operands): Remove many redundant

        operands.  Update opcode table as appropriate.
        (IMM32): Add MN10300_OPERAND_SPLIT flag.
        (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.

2 files changed, 69 insertions, 77 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9791518..da8546a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+Wed Nov  6 13:42:32 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300-opc.c (mn10300_operands): Remove many redundant
+	operands.  Update opcode table as appropriate.
+	(IMM32): Add MN10300_OPERAND_SPLIT flag.
+	(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
+
 Tue Nov  5 13:26:58 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c
index 7a6e333..8b09f94 100644
--- a/opcodes/mn10300-opc.c
+++ b/opcodes/mn10300-opc.c
@@ -66,18 +66,9 @@ const struct mn10300_operand mn10300_operands[] = {
   {16, 0, MN10300_OPERAND_PROMOTE},
 
 #define IMM32    (IMM16+1)
-  {32, 0, 0},
+  {32, 0, MN10300_OPERAND_SPLIT},
 
-#define D8    (IMM32+1)
-  {8, 0, MN10300_OPERAND_PROMOTE},
-
-#define D16    (D8+1)
-  {16, 0, MN10300_OPERAND_PROMOTE},
-
-#define D32    (D16+1)
-  {32, 0, 0},
-
-#define SP    (D32+1)
+#define SP    (IMM32+1)
   {8, 0, MN10300_OPERAND_SP},
 
 #define PSW    (SP+1)
@@ -86,13 +77,7 @@ const struct mn10300_operand mn10300_operands[] = {
 #define MDR    (PSW+1)
   {0, 0, MN10300_OPERAND_MDR},
 
-#define ABS16 (MDR+1)
-  {16, 0, MN10300_OPERAND_PROMOTE},
-
-#define ABS32 (ABS16+1)
-  {32, 0, 0},
-
-#define DI (ABS32+1)
+#define DI (MDR+1)
   {2, 2, MN10300_OPERAND_DREG},
 
 #define SD8    (DI+1)
@@ -169,91 +154,91 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM0), DN1}},
 { "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
 { "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
-{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
-{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(D8, SP), DN0}},
-{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
-{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
+{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
+{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), DN0}},
+{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
+{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
 { "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
-{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
-{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
+{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
+{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
 { "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM0), AN1}},
-{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(D8, AM0), AN1}},
-{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(D16, AM0), AN1}},
-{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), AN1}},
-{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(D8, SP), AN0}},
-{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), AN0}},
-{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), AN0}},
+{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(SD8,AM0), AN1}},
+{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), AN1}},
+{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), AN1}},
+{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), AN0}},
+{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), AN0}},
+{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), AN0}},
 { "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM0), AN2}},
-{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(ABS16), AN0}},
-{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(ABS32), AN0}},
+{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(IMM16), AN0}},
+{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(IMM32), AN0}},
 { "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM0), SP}},
 { "mov",	0x60,		0xf0,		FMT_S0, {DM1, MEM(AN0)}},
 { "mov",	0xf81000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
 { "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
-{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
-{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(D8, SP)}},
-{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
-{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
+{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
+{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(IMM8, SP)}},
+{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
+{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
 { "mov",	0xf340,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
-{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
-{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},
+{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
+{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},
 { "mov",	0xf010,		0xfff0,		FMT_D0, {AM1, MEM(AN0)}},
 { "mov",	0xf83000,	0xfff000,	FMT_D1, {AM1, MEM2(SD8, AN0)}},
 { "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM1, MEM2(SD16, AN0)}},
-{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(D32, AN0)}},
-{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(D8, SP)}},
-{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(D16, SP)}},
-{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(D32, SP)}},
+{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(IMM32,AN0)}},
+{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(IMM8, SP)}},
+{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(IMM16, SP)}},
+{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(IMM32, SP)}},
 { "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM2, MEM2(DI, AN0)}},
-{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(ABS16)}},
-{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(ABS32)}},
+{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(IMM16)}},
+{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(IMM32)}},
 { "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN0)}},
 { "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN0}},
-{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
+{ "mov",	0xfccc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
 { "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN0}},
 { "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
 
 { "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
 { "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
 { "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
-{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
-{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN0}},
-{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
-{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
+{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
+{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
+{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
+{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
 { "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
-{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
-{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
+{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
+{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
 { "movbu",	0xf050,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
 { "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
 { "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
-{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
-{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(D8, SP)}},
-{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
-{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
+{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
+{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
+{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
+{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
 { "movbu",	0xf440,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
-{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
-{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},
+{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
+{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},
 
 { "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
 { "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
 { "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
-{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
-{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN0}},
-{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
-{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
+{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
+{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
+{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
+{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
 { "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
-{ "movhu",	0x380000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
-{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
+{ "movhu",	0x380000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
+{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
 { "movhu",	0xf070,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
 { "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
 { "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
-{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
-{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(D8, SP)}},
-{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
-{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
+{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
+{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
+{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
+{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
 { "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
-{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
-{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},
+{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
+{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},
 
 { "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN0}},
 { "extb",	0x10, 		0xfc,		FMT_S0, {DN0}},
@@ -328,15 +313,15 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN0}},
 { "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
 { "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
-{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
+{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8, MEM(IMM32)}},
 { "btst",	0xfaf80000,	0xfffc0000,	FMT_D2,
 					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 { "bset",	0xf080,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
-{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
+{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8, MEM(IMM32)}},
 { "bset",	0xfaf00000,	0xfffc0000,	FMT_D2,
 					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 { "bclr",	0xf090,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
-{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
+{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8, MEM(IMM32)}},
 { "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8,
 					MEM2(SD8N_SHIFT8,AN0)}},
 
@@ -381,13 +366,13 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},
 
 { "jmp",	0xf0f4,		0xfffc,		FMT_D0, {AN0}},
-{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {D16}},
-{ "jmp",	0xdc0000,	0xff0000,	FMT_S4, {D32}},
+{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {IMM16}},
+{ "jmp",	0xdc0000,	0xff0000,	FMT_S4, {IMM32}},
 { "call",	0xcd000000,	0xff000000,	FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
-{ "call",	0xdd000000,	0xff000000,	FMT_S6, {D32,IMM8,IMM8}},
+{ "call",	0xdd000000,	0xff000000,	FMT_S6, {IMM32,IMM8,IMM8}},
 { "calls",	0xf0f0,		0xfffc,		FMT_D0, {AN0}},
-{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {D16}},
-{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {D32}},
+{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {IMM16}},
+{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {IMM32}},
 
 { "ret",	0xdf0000,	0xff00000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
 { "retf",	0xde0000,	0xff00000,	FMT_S2, {IMM8_SHIFT8, IMM8}},