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| author | Jeff Law <law@redhat.com> | 1996-08-23 17:35:11 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-08-23 17:35:11 +0000 |
| commit | e41c99bd119447d1b4b5784d9286e7e0b0b31dc0 (patch) | |
| tree | 74c07052405275ddbec38df99c3ed53b7d403b38 /opcodes | |
| parent | 4fc797ff5cb66a7ee878820eea2c14f39341cd10 (diff) | |
| download | gdb-e41c99bd119447d1b4b5784d9286e7e0b0b31dc0.zip gdb-e41c99bd119447d1b4b5784d9286e7e0b0b31dc0.tar.gz gdb-e41c99bd119447d1b4b5784d9286e7e0b0b31dc0.tar.bz2 | |
* v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
register source and destination operands.
(v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
More parsing fixes.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/v850-opc.c | 10 |
2 files changed, 12 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6c46ffa..41521e8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,10 @@ start-sanitize-v850 Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) + * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system + register source and destination operands. + (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". + * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix same thinko in "trap" opcode. diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index a445a67..9047701 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -72,6 +72,12 @@ const struct v850_operand v850_operands[] = { #define D8 (CCCC+1) { 8, 0, 0, 0, 0 }, +/* System register operands. */ +#define SR1 (D8+1) + { 5, 0, 0, 0, V850_OPERAND_SRG }, + +#define SR2 (SR1+1) + { 5, 11, 0, 0, V850_OPERAND_SRG }, } ; @@ -220,8 +226,8 @@ const struct v850_opcode v850_opcodes[] = { { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 4 }, { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 4 }, { "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5U}, 4 }, -{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), IF1, 4 }, -{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), IF1, 4 }, +{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {R1,SR2}, 4 }, +{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {SR1,R2}, 4 }, { "nop", one(0x00), one(0xff), {0}, 2 }, } ; |