R_MICROMIPS_GPREL7_S2

This reloc is meant for the 16-bit LWGP instruction, 0x6400/0xfc00
match/mask encoding in `micromips_opcodes'.  It is correctly specified
to operate on a half-word by the howtos in elf32-mips.c, elfn32-mips.c
and elf64-mips.c, but is incorrectly subject to shuffle/unshuffle in
code like _bfd_mips_elf32_gprel16_reloc.

Current behaviour when applying the reloc to .byte 0x11,0x22,0x33,0x44
is to apply the reloc to byte 0x22 when big-endian, and to byte 0x33
when little-endian.  Big-endian behaviour is unchanged after this
patch and little-endian correctly applies the reloc to byte 0x11.

The patch also corrects REL addend extraction from section contents,
and overflow checking.  gold had all of the bfd problems with this
reloc and additionally did not apply the rightshift by two.

bfd/
	* elfxx-mips.c (micromips_reloc_shuffle_p): Return false for
	R_MICROMIPS_GPREL7_S2.
	(mips_elf_calculate_relocation): Correct sign extension and
	overflow calculation for R_MICROMIPS_GPREL7_S2.
	(_bfd_mips_elf_relocate_section): Update small-data overflow
	message.
gold/
	* mips.cc (Mips_relocate_functions::should_shuffle_micromips_reloc):
	Return false for R_MICROMIPS_GPREL7_S2.
	(Mips_relocate_functions::mips_reloc_unshuffle): Update comment.
	(Mips_relocate_functions::relgprel): Remove R_MICROMIPS_GPREL7_S2
	handling.
	(Mips_relocate_functions::relgprel7): New function.
	(Target_mips::Relocate::relocate): Adjust to suit.
ld/
	* testsuite/ld-mips-elf/reloc-4.d: Adjust expected error.
	* testsuite/ld-mips-elf/reloc-5.d: Likewise.

0 files changed, 0 insertions, 0 deletions