RISC-V: Add load/store instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	load/store instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLBV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

1 files changed, 44 insertions, 0 deletions

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4c2a9b5..54c1e8a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2237,6 +2237,50 @@ const struct riscv_opcode riscv_opcodes[] =
 /* Vendor-specific (T-Head) XTheadVector instructions.  */
 {"th.vsetvl",     0, INSN_CLASS_XTHEADVECTOR,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
 {"th.vsetvli",    0, INSN_CLASS_XTHEADVECTOR,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+{"th.vlb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBV, MASK_TH_VLBV, match_opcode, INSN_DREF },
+{"th.vlh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHV, MASK_TH_VLHV, match_opcode, INSN_DREF },
+{"th.vlw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWV, MASK_TH_VLWV, match_opcode, INSN_DREF },
+{"th.vlbu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
+{"th.vlhu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
+{"th.vlwu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
+{"th.vle.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
+{"th.vsb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
+{"th.vsh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
+{"th.vsw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
+{"th.vse.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
+{"th.vlsb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSBV, MASK_TH_VLSBV, match_opcode, INSN_DREF },
+{"th.vlsh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSHV, MASK_TH_VLSHV, match_opcode, INSN_DREF },
+{"th.vlsw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSWV, MASK_TH_VLSWV, match_opcode, INSN_DREF },
+{"th.vlsbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
+{"th.vlshu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
+{"th.vlswu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
+{"th.vlse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
+{"th.vssb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
+{"th.vssh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
+{"th.vssw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
+{"th.vsse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
+{"th.vlxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXBV, MASK_TH_VLXBV, match_opcode, INSN_DREF },
+{"th.vlxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXHV, MASK_TH_VLXHV, match_opcode, INSN_DREF },
+{"th.vlxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXWV, MASK_TH_VLXWV, match_opcode, INSN_DREF },
+{"th.vlxbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF },
+{"th.vlxhu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"th.vlxwu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF },
+{"th.vlxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF },
+{"th.vsxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF },
+{"th.vsxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF },
+{"th.vsxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF },
+{"th.vsxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF },
+{"th.vsuxb.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXBV, MASK_TH_VSUXBV, match_opcode, INSN_DREF },
+{"th.vsuxh.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXHV, MASK_TH_VSUXHV, match_opcode, INSN_DREF },
+{"th.vsuxw.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXWV, MASK_TH_VSUXWV, match_opcode, INSN_DREF },
+{"th.vsuxe.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXEV, MASK_TH_VSUXEV, match_opcode, INSN_DREF },
+{"th.vlbff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBFFV, MASK_TH_VLBFFV, match_opcode, INSN_DREF },
+{"th.vlhff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHFFV, MASK_TH_VLHFFV, match_opcode, INSN_DREF },
+{"th.vlwff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWFFV, MASK_TH_VLWFFV, match_opcode, INSN_DREF },
+{"th.vlbuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+{"th.vlhuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+{"th.vlwuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
+{"th.vleff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },