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| author | Jim Wilson <jimw@sifive.com> | 2023-06-01 12:10:16 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-06-01 12:25:08 +0800 |
| commit | ec2260af61501798d00e41c3180c63d25b11439c (patch) | |
| tree | 7ffe0055a6556d67d4b974e41c37205626268f39 /opcodes | |
| parent | 20ef84ed2abb990da08d90e1c978f96d29f40606 (diff) | |
| download | gdb-ec2260af61501798d00e41c3180c63d25b11439c.zip gdb-ec2260af61501798d00e41c3180c63d25b11439c.tar.gz gdb-ec2260af61501798d00e41c3180c63d25b11439c.tar.bz2 | |
RISC-V: PR30449, Add lga assembler macro support.
Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539
Added new load address pseudo instruction which is always expanded to GOT
access, no matter the .option rvc is set or not.
gas/
PR 30449
* config/tc-riscv.c (macro): Add M_LGA support.
* testsuite/gas/riscv/la-variants.d: New.
* testsuite/gas/riscv/la-variants.s: New.
include/
PR 30449
* opcode/riscv.h (M_LGA): New.
opcodes/
PR 30449
* riscv-opc.c (riscv_opcodes): Add lga support.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1c3d9b0..57e7b90 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -405,6 +405,7 @@ const struct riscv_opcode riscv_opcodes[] = {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"la", 0, INSN_CLASS_I, "d,B", 0, (int) M_LA, match_never, INSN_MACRO }, {"lla", 0, INSN_CLASS_I, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO }, +{"lga", 0, INSN_CLASS_I, "d,B", 0, (int) M_LGA, match_never, INSN_MACRO }, {"la.tls.gd", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, {"la.tls.ie", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, {"neg", 0, INSN_CLASS_I, "d,t", MATCH_SUB, MASK_SUB|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ |