aboutsummaryrefslogtreecommitdiff
path: root/opcodes
diff options
context:
space:
mode:
authorDavid Guillen Fandos <david@davidgf.net>2023-06-15 04:45:03 +0100
committerMaciej W. Rozycki <macro@orcam.me.uk>2023-06-15 04:45:03 +0100
commitd29b94fc9f365de8002a9566df5bd8a45c7c8f1d (patch)
treec002263374179183c7a946db845df4df087e3ce2 /opcodes
parentdf18f71b565c29f6f1ebd385cb1aed97d00e9660 (diff)
downloadgdb-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.zip
gdb-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.tar.gz
gdb-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.tar.bz2
Add rotation instructions to MIPS Allegrex CPU
The Allegrex CPU supports bit rotation instructions as described in the MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU). Signed-off-by: David Guillen Fandos <david@davidgf.net>
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/mips-opc.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 3c48c0c..8eecae9 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1802,13 +1802,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 },
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 },
-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 },
-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 },
-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 },
+{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT, 0 },
+{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL, SMT, 0 },
+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, SMT, 0 },
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },