diff options
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-06-27 07:22:49 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-06-27 07:24:43 -0600 |
| commit | b625eff8a2346fe1107aa4ab7bbf4302f2c2136e (patch) | |
| tree | 9e11fce586187e074473ba6d38ea3e2be64c8697 /opcodes | |
| parent | 15d842846d1fd79e141b1eddc9f648a8200223da (diff) | |
| download | gdb-b625eff8a2346fe1107aa4ab7bbf4302f2c2136e.zip gdb-b625eff8a2346fe1107aa4ab7bbf4302f2c2136e.tar.gz gdb-b625eff8a2346fe1107aa4ab7bbf4302f2c2136e.tar.bz2 | |
RISC-V: Support Zicond extension
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-rc2.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
for the proposed specification and usage details.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Recognize
INSN_CLASS_ZICOND.
(riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.
gas/ChangeLog:
* testsuite/gas/riscv/zicond.d: New test.
* testsuite/gas/riscv/zicond.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
(MASK_CZERO_EQZ): Define.
(MATCH_CZERO_NEZ): Define,
(MASK_CZERO_NEZ): Define.
(DECLARE_INSN): Add czero.eqz and czero.nez.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZICOND.
opcodes/ChangeLog:
* riscv-opc.c: Add czero.eqz and czero.nez.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 57e7b90..2b2dce1 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -936,6 +936,10 @@ const struct riscv_opcode riscv_opcodes[] = {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, +/* Zicond instructions. */ +{"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, +{"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, + /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, |