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authorChristoph Müllner <christoph.muellner@vrull.eu>2023-06-30 22:43:46 +0200
committerJeff Law <jlaw@ventanamicro>2023-07-01 07:28:40 -0600
commit9d469329d229da8e2a6d7b70a2be3988aa45a277 (patch)
tree1e6e7cbaf08250da688d92b21f32a21f70c614ae /opcodes
parentc0a98a853d5ccde35dca20ad5d7cea0a70e16d56 (diff)
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RISC-V: Add support for the Zvkg ISA extension
Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/riscv-opc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 19a7290..b2aadb1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1908,6 +1908,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+/* Zvkg instructions. */
+{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
+{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },