x86: flag bad EVEX masking for miscellaneous insns

Masking is not permitted for certain further insns, not falling in any
of the earlier categories. Introduce the Y macro (not expanding to any
output) to flag such cases.

Note that in a few cases entries already covered otherwise are converted
as well, to continue to allow sharing of the string literals.

6 files changed, 51 insertions, 44 deletions

diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h
index b3af48e..ec839e6 100644
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -9,22 +9,22 @@
   /* MOD_EVEX_0F3828_P_1 */
   {
     { Bad_Opcode },
-    { "vpmovm2%BW",	{ XM, MaskE }, 0 },
+    { "vpmovm2Y%BW",	{ XM, MaskE }, 0 },
   },
   /* MOD_EVEX_0F382A_P_1_W_1 */
   {
     { Bad_Opcode },
-    { "vpbroadcastmb2q",	{ XM, MaskE }, 0 },
+    { "vpbroadcastmb2qY",	{ XM, MaskE }, 0 },
   },
   /* MOD_EVEX_0F3838_P_1 */
   {
     { Bad_Opcode },
-    { "vpmovm2%DQ",	{ XM, MaskE }, 0 },
+    { "vpmovm2Y%DQ",	{ XM, MaskE }, 0 },
   },
   /* MOD_EVEX_0F383A_P_1_W_0 */
   {
     { Bad_Opcode },
-    { "vpbroadcastmw2d",	{ XM, MaskE }, 0 },
+    { "vpbroadcastmw2dY",	{ XM, MaskE }, 0 },
   },
   /* MOD_EVEX_0F385A */
   {
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index a6fdca7..c78c1b7 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -42,9 +42,9 @@
   /* PREFIX_EVEX_0F7B */
   {
     { Bad_Opcode },
-    { "vcvtusi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "vcvtusi2ssY{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
     { VEX_W_TABLE (EVEX_W_0F7B_P_2) },
-    { "vcvtusi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
+    { "vcvtusi2sdY{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
   },
   /* PREFIX_EVEX_0F7E */
   {
@@ -166,7 +166,7 @@
   /* PREFIX_EVEX_0F3829 */
   {
     { Bad_Opcode },
-    { "vpmov%BW2m",	{ MaskG, EXx }, 0 },
+    { "vpmov%BW2mY",	{ MaskG, EXx }, 0 },
     { VEX_W_TABLE (EVEX_W_0F3829_P_2) },
   },
   /* PREFIX_EVEX_0F382A */
@@ -220,7 +220,7 @@
   /* PREFIX_EVEX_0F3839 */
   {
     { Bad_Opcode },
-    { "vpmov%DQ2m",	{ MaskG, EXx }, 0 },
+    { "vpmov%DQ2mY",	{ MaskG, EXx }, 0 },
     { "%XEvpmins%DQ",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F383A */
@@ -248,7 +248,7 @@
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
+    { "vp2intersectY%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_0F3872 */
   {
@@ -357,7 +357,7 @@
   /* PREFIX_EVEX_MAP5_2A */
   {
     { Bad_Opcode },
-    { "vcvtsi2sh{%LQ|}",        { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "vcvtsi2shY{%LQ|}",        { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
   },
   /* PREFIX_EVEX_MAP5_2C */
   {
@@ -371,11 +371,11 @@
   },
   /* PREFIX_EVEX_MAP5_2E */
   {
-    { "vucomis%XH",       { XMScalar, EXw, EXxEVexS }, 0 },
+    { "vucomisY%XH",       { XMScalar, EXw, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_MAP5_2F */
   {
-    { "vcomis%XH",        { XMScalar, EXw, EXxEVexS }, 0 },
+    { "vcomisY%XH",        { XMScalar, EXw, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_MAP5_51 */
   {
@@ -447,7 +447,7 @@
   /* PREFIX_EVEX_MAP5_7B */
   {
     { Bad_Opcode },
-    { "vcvtusi2sh{%LQ|}",       { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "vcvtusi2shY{%LQ|}",       { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
     { "vcvtp%XH2qq",    { XM, EXxmmqdh, EXxEVexR }, 0 },
   },
   /* PREFIX_EVEX_MAP5_7C */
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h
index c0f55c3..0665c9a 100644
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -23,11 +23,11 @@
     { Bad_Opcode },
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F73_R_2) },
-    { "%XEvpsrldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsrldqY",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F73_R_6) },
-    { "%XEvpslldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpslldqY",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* REG_EVEX_0F38C6_M_0_L_2 */
   {
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index ba3b195..5a0352e 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -293,7 +293,7 @@
   },
   /* EVEX_W_0F382A_P_2 */
   {
-    { "%XEvmovntdqa",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovntdqaY",	{ XM, EXEvexXNoBcst }, 0 },
   },
   /* EVEX_W_0F382B */
   {
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 65935a3..8350cd3 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -278,7 +278,7 @@ static const struct dis386 evex_table[][256] = {
     { VEX_W_TABLE (EVEX_W_0FF3) },
     { VEX_W_TABLE (EVEX_W_0FF4) },
     { "%XEvpmaddwd",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "%XEvpsadbw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsadbwY",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     /* F8 */
     { "%XEvpsubb",	{ XM, Vex, EXx }, PREFIX_DATA },
@@ -540,10 +540,10 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "%XEvaesenc",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "%XEvaesenclast",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "%XEvaesdec",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "%XEvaesdeclast",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesencY",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesenclastY", { XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesdecY",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA },
     /* E0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -660,7 +660,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3A42) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A43) },
-    { "%XEvpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
+    { "%XEvpclmulqdqY",	{ XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -998,7 +998,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vmovw", { XMScalar, Edw }, PREFIX_DATA },
+    { "vmovwY", { XMScalar, Edw }, PREFIX_DATA },
     { Bad_Opcode },
     /* 70 */
     { Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index d5e3547..ef8d6b2 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1806,7 +1806,7 @@ struct dis386 {
    'V' unused.
    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
    'X' => print 's', 'd' depending on data16 prefix (for XMM)
-   'Y' unused.
+   'Y' => no output, mark EVEX.aaa != 0 as bad.
    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
    '!' => change condition from true to false or from false to true.
    '%' => add 1 upper case letter to the macro.
@@ -1828,6 +1828,8 @@ struct dis386 {
    "XV" => print "{vex} " pseudo prefix
    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
 	   is used by an EVEX-encoded (AVX512VL) instruction.
+   "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
+   "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
 	   being false, or no operand at all in 64bit mode, or if suffix_always
 	   is true.
@@ -3719,9 +3721,9 @@ static const struct dis386 prefix_table[][4] = {
   /* PREFIX_VEX_0F2A */
   {
     { Bad_Opcode },
-    { "%XEvcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "%XEvcvtsi2ssY{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
     { Bad_Opcode },
-    { "%XEvcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
+    { "%XEvcvtsi2sdY{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
   },
 
   /* PREFIX_VEX_0F2C */
@@ -3742,16 +3744,16 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F2E */
   {
-    { "%XEvucomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvucomisYX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "%XEvucomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvucomisYX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F2F */
   {
-    { "%XEvcomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvcomisYX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "%XEvcomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvcomisYX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -7004,32 +7006,32 @@ static const struct dis386 vex_table[][256] = {
 static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
   {
-    { "%XEvmovlpX",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovlpYX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F12_P_0_M_1 */
   {
-    { "%XEvmovhlp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovhlpY%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F13_M_0 */
   {
-    { "%XEvmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovlpYX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
   {
-    { "%XEvmovhpX",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovhpYX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F16_P_0_M_1 */
   {
-    { "%XEvmovlhp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovlhpY%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F17_M_0 */
   {
-    { "%XEvmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovhpYX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F41 */
@@ -7081,7 +7083,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F6E */
   {
-    { "%XEvmovK",	{ XMScalar, Edq }, PREFIX_DATA },
+    { "%XEvmovYK",	{ XMScalar, Edq }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F77 */
@@ -7092,7 +7094,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F7E_P_1 */
   {
-    { "%XEvmovq",	{ XMScalar, EXq }, 0 },
+    { "%XEvmovqY",	{ XMScalar, EXq }, 0 },
   },
 
   /* VEX_LEN_0F7E_P_2 */
@@ -7142,7 +7144,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0FC4 */
   {
-    { "%XEvpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
+    { "%XEvpinsrwY",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FC5 */
@@ -7152,7 +7154,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0FD6 */
   {
-    { "%XEvmovq",	{ EXqS, XMScalar }, PREFIX_DATA },
+    { "%XEvmovqY",	{ EXqS, XMScalar }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FF7 */
@@ -7302,17 +7304,17 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A20 */
   {
-    { "%XEvpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
+    { "%XEvpinsrbY",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A21 */
   {
-    { "%XEvinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
+    { "%XEvinsertpsY",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A22 */
   {
-    { "%XEvpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
+    { "%XEvpinsrYK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A30 */
@@ -11126,7 +11128,12 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
 	    *ins->obufp++ = 's';
 	  break;
 	case 'Y':
-	  if (l == 1 && last[0] == 'X')
+	  if (l == 0)
+	    {
+	      if (ins->vex.mask_register_specifier)
+		ins->illegal_masking = true;
+	    }
+	  else if (l == 1 && last[0] == 'X')
 	    {
 	      if (!ins->need_vex)
 		abort ();