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authorTamar Christina <tamar.christina@arm.com>2019-02-07 17:12:23 +0000
committerTamar Christina <tamar.christina@arm.com>2019-02-07 17:20:41 +0000
commitf7dd2fb2e2b750f0fb9dedaf885c17bc6beef1f7 (patch)
treee94bcaf98363e67b9cf0785d0d96d7d6c9f41658 /opcodes
parentbd756351a6d3dcff9915c88c26dc0a5811907f90 (diff)
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Arm: Backport hlt to all architectures.
The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c3
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2523b31..8427130 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
2019-02-07 Tamar Christina <tamar.christina@arm.com>
+ * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
+
+2019-02-07 Tamar Christina <tamar.christina@arm.com>
+
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 4885227..71d7c52 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1788,7 +1788,8 @@ static const struct opcode32 arm_opcodes[] =
/* V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0x0320f005, 0x0fffffff, "sevl"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+ /* Defined in V8 but is in NOP space so available to all arch. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},