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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-05-01 12:59:24 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-05-01 12:59:24 +0000 |
| commit | 9344ff29511f1014a188c089a82d4415cfcb30cb (patch) | |
| tree | d38acd907b27f6abc979c48b35ca53d8ca16792e /opcodes | |
| parent | 3764ce598cadc511785fb23230bf104ccbadc368 (diff) | |
| download | gdb-9344ff29511f1014a188c089a82d4415cfcb30cb.zip gdb-9344ff29511f1014a188c089a82d4415cfcb30cb.tar.gz gdb-9344ff29511f1014a188c089a82d4415cfcb30cb.tar.bz2 | |
gas/config/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check suffix for crc32 in
Intel mdoe.
(process_suffix): Default the suffix of 8bit crc32 to
BYTE_MNEM_SUFFIX.
(check_byte_reg): Skip check for 8bit crc32.
gas/testsuite/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/crc32-intel.d: New file.
* gas/i386/crc32.d:Likewise.
* gas/i386/crc32.s:Likewise.
* gas/i386/x86-64-crc32-intel.d:Likewise.
* gas/i386/x86-64-crc32.d:Likewise.
* gas/i386/x86-64-crc32.s:Likewise.
* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
and x86-64-crc32-intel.
opcodes/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
check data size prefix in 16bit mode.
* i386-opc.c (i386_optab): Default crc32 to non-8bit and
support Intel mode.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 12 | ||||
| -rw-r--r-- | opcodes/i386-opc.c | 6 |
3 files changed, 17 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e751f9f..afdba13 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2007-05-01 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and + check data size prefix in 16bit mode. + + * i386-opc.c (i386_optab): Default crc32 to non-8bit and + support Intel mode. + 2007-04-30 Mark Salter <msalter@redhat.com> * frv-desc.c: Regenerate. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index aebb71e..2f26e06 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -6390,13 +6390,11 @@ CRC32_Fixup (int bytemode, int sizeflag) USED_REX (REX_W); if (rex & REX_W) *p++ = 'q'; - else if ((prefixes & PREFIX_DATA)) - { - *p++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } + else if (sizeflag & DFLAG) + *p++ = intel_syntax ? 'd' : 'l'; else - *p++ = 'l'; + *p++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); @@ -6434,5 +6432,5 @@ CRC32_Fixup (int bytemode, int sizeflag) } } else - OP_E (v_mode, sizeflag); + OP_E (bytemode, sizeflag); } diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c index a374b65..e03152c 100644 --- a/opcodes/i386-opc.c +++ b/opcodes/i386-opc.c @@ -1442,10 +1442,12 @@ const template i386_optab[] = {"pcmpestrm", 3, 0x660f3a60,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistri", 3, 0x660f3a63,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"crc32b", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8|ByteMem, Reg32|Reg64, 0 } }, -{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8, Reg32|Reg64, 0 } }, +/* We put non-8bit version before 8bit so that crc32 with memory operand + defaults to non-8bit. */ {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } }, {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm, { Reg8|ByteMem, Reg32, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } }, /* AMD 3DNow! instructions. */ |