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authorJim Wilson <jimw@sifive.com>2018-02-22 11:28:51 -0800
committerJim Wilson <jimw@sifive.com>2018-02-22 11:28:51 -0800
commit0bccfb2994d307601ceba5c3a6223b7ca7cf5338 (patch)
tree36367bdd92845e6ff48c3c40e4b7c039991fa57b /opcodes
parent7bdf778b10b1ab85553a31c104097073214f6430 (diff)
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RISC-V: Make disassebler work for --enable-targets=all config.
opcodes/ * disassemble.c (ARCH_riscv): Define if ARCH_all.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/disassemble.c1
2 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b4b4cbb..325972f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-02-22 Shea Levy <shea@shealevy.com>
+
+ * disassemble.c (ARCH_riscv): Define if ARCH_all.
+
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add {rex},
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index ae48f536..78f0995 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -76,6 +76,7 @@
#define ARCH_pj
#define ARCH_powerpc
#define ARCH_pru
+#define ARCH_riscv
#define ARCH_rs6000
#define ARCH_rl78
#define ARCH_rx