/bfd:

2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* archures.c: Add AVR XMEGA architecture information.
	* cpu-avr.c (arch_info_struct): Likewise.
	* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
	(elf32_avr_object_p): Likewise.

/gas:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
	(AVR_INSN): Change definition to match.
	(avr_opcodes): Likewise, change to match.
	(mcu_types): Add XMEGA architecture names and new XMEGA device names.
	(md_show_usage): Add XMEGA architecture names.
	(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
	Add support for SPM Z+ instruction.
	* doc/c-avr.texi: Add documentation for XMEGA architectures and
	devices.

/include/opcode:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
	New instruction set flags.
	(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.

/ld:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
	(eavrxmega?.c): Likewise.
	* configure.tgt (targ_extra_emuls): Likewise.
	* emulparams/avrxmega1.sh: New file.
	* emulparams/avrxmega2.sh: Likewise.
	* emulparams/avrxmega3.sh: Likewise.
	* emulparams/avrxmega4.sh: Likewise.
	* emulparams/avrxmega5.sh: Likewise.
	* emulparams/avrxmega6.sh: Likewise.
	* emulparams/avrxmega7.sh: Likewise.
	* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
	Add avrxmega6, avrxmega7 to list of architectures for no stubs.

/opcodes:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	post-increment to support LPM Z+ instruction. Add support for 'E'
	constraint for DES instruction.
	(print_insn_avr): Adjust calls to avr_operand. Rename variable.

2 files changed, 30 insertions, 8 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0300c26..6ef4525 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
+	post-increment to support LPM Z+ instruction. Add support for 'E'
+	constraint for DES instruction.
+	(print_insn_avr): Adjust calls to avr_operand. Rename variable.
+
 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 
 	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
diff --git a/opcodes/avr-dis.c b/opcodes/avr-dis.c
index 976c371..85d7ab3 100644
--- a/opcodes/avr-dis.c
+++ b/opcodes/avr-dis.c
@@ -50,7 +50,7 @@ static const char * comment_start = "0x";
 
 static int
 avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
-             char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
+             char *opcode_str, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
 {
   int ok = 1;
   *sym = 0;
@@ -118,8 +118,18 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
 
     case 'z':
       *buf++ = 'Z';
-      if (insn & 0x1)
+
+      /* Check for post-increment. */
+      char *s;
+      for (s = opcode_str; *s; ++s)
+        {
+          if (*s == '+')
+            {
 	*buf++ = '+';
+              break;
+            }
+        }
+
       *buf = '\0';
       if (AVR_UNDEF_P (insn))
 	sprintf (comment, _("undefined"));
@@ -227,6 +237,10 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
       }
       break;
       
+    case 'E':
+      sprintf (buf, "%d", (insn >> 4) & 15);
+      break;
+      
     case '?':
       *buf = '\0';
       break;
@@ -331,7 +345,8 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
 
   if (opcode->name)
     {
-      char *op = opcode->constraints;
+      char *constraints = opcode->constraints;
+      char *opcode_str = opcode->opcode;
 
       insn2 = 0;
       ok = 1;
@@ -342,14 +357,14 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
 	  cmd_len = 4;
 	}
 
-      if (*op && *op != '?')
+      if (*constraints && *constraints != '?')
 	{
-	  int regs = REGISTER_P (*op);
+	  int regs = REGISTER_P (*constraints);
 
-	  ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);
+	  ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1, comment1, 0, &sym_op1, &sym_addr1);
 
-	  if (ok && *(++op) == ',')
-	    ok = avr_operand (insn, insn2, addr, *(++op), op2,
+	  if (ok && *(++constraints) == ',')
+	    ok = avr_operand (insn, insn2, addr, *(++constraints), opcode_str, op2,
 			      *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
 	}
     }