[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline

This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL

gas/ChangeLog:

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (TOGGLE_BIT): New.
	(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
	csinv, csneg, cset, csetm and csel.
	(operand_parse_code): New OP_RR_ZR.
	(parse_operand): Handle case for OP_RR_ZR.
	(do_t_cond): New.
	(insns): New instructions for cinc, cinv, cneg, csinc,
	csinv, csneg, cset, csetm, csel.
	* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
	* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
	* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
	* testsuite/gas/arm/armv8_1-m-cond.d: New test.
	* testsuite/gas/arm/armv8_1-m-cond.s: New test.

opcodes/ChangeLog:

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (enum mve_instructions): New enum
	for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
	and cneg.
	(mve_opcodes): New instructions as above.
	(is_mve_encoding_conflict): Add cases for csinc, csinv,
	csneg and csel.
	(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.

2 files changed, 99 insertions, 0 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e6950ac..c336a1a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,15 @@
 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 
+	* arm-dis.c (enum mve_instructions): New enum
+	for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
+	and cneg.
+	(mve_opcodes): New instructions as above.
+	(is_mve_encoding_conflict): Add cases for csinc, csinv,
+	csneg and csel.
+	(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
+
+2019-05-21  Sudakshina Das  <sudi.das@arm.com>
+
 	* arm-dis.c (emun mve_instructions): Updated for new instructions.
 	(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 	sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ab99fb7..ad65ffa 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -281,6 +281,15 @@ enum mve_instructions
   MVE_SRSHR,
   MVE_SQSHLL,
   MVE_SQSHL,
+  MVE_CINC,
+  MVE_CINV,
+  MVE_CNEG,
+  MVE_CSINC,
+  MVE_CSINV,
+  MVE_CSET,
+  MVE_CSETM,
+  MVE_CSNEG,
+  MVE_CSEL,
   MVE_NONE
 };
 
@@ -2060,6 +2069,8 @@ static const struct opcode32 neon_opcodes[] =
    %<bitfield>r		print as an ARM register
    %<bitfield>d		print the bitfield in decimal
    %<bitfield>A		print accumulate or not
+   %<bitfield>c		print bitfield as a condition code
+   %<bitfield>C		print bitfield as an inverted condition code
    %<bitfield>Q		print as a MVE Q register
    %<bitfield>F		print as a MVE S register
    %<bitfield>Z		as %<>r but r15 is ZR instead of PC and r13 is
@@ -3400,6 +3411,51 @@ static const struct mopcode32 mve_opcodes[] =
    0xea500f1f, 0xfff08f3f,
    "urshr%c\t%16-19S, %j"},
 
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSINC,
+   0xea509000, 0xfff0f000,
+   "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSINV,
+   0xea50a000, 0xfff0f000,
+   "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSET,
+   0xea5f900f, 0xfffff00f,
+   "cset\t%8-11S, %4-7C"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSETM,
+   0xea5fa00f, 0xfffff00f,
+   "csetm\t%8-11S, %4-7C"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSEL,
+   0xea508000, 0xfff0f000,
+   "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CSNEG,
+   0xea50b000, 0xfff0f000,
+   "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CINC,
+   0xea509000, 0xfff0f000,
+   "cinc\t%8-11S, %16-19Z, %4-7C"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CINV,
+   0xea50a000, 0xfff0f000,
+   "cinv\t%8-11S, %16-19Z, %4-7C"},
+
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   MVE_CNEG,
+   0xea50b000, 0xfff0f000,
+   "cneg\t%8-11S, %16-19Z, %4-7C"},
+
   {ARM_FEATURE_CORE_LOW (0),
    MVE_NONE,
    0x00000000, 0x00000000, 0}
@@ -5653,6 +5709,30 @@ is_mve_encoding_conflict (unsigned long given,
       else
 	return FALSE;
 
+    case MVE_CSINC:
+    case MVE_CSINV:
+      {
+	unsigned long rm, rn;
+	rm = arm_decode_field (given, 0, 3);
+	rn = arm_decode_field (given, 16, 19);
+	/* CSET/CSETM.  */
+	if (rm == 0xf && rn == 0xf)
+	  return TRUE;
+	/* CINC/CINV.  */
+	else if (rn == rm && rn != 0xf)
+	  return TRUE;
+      }
+    /* Fall through.  */
+    case MVE_CSEL:
+    case MVE_CSNEG:
+      if (arm_decode_field (given, 0, 3) == 0xd)
+	return TRUE;
+      /* CNEG.  */
+      else if (matched_insn == MVE_CSNEG)
+	if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
+	  return TRUE;
+      return FALSE;
+
     default:
     case MVE_VADD_FP_T1:
     case MVE_VADD_FP_T2:
@@ -9264,6 +9344,15 @@ print_insn_mve (struct disassemble_info *info, long given)
 			      func (stream, "%s", arm_regnames[value]);
 			    break;
 
+			  case 'c':
+			    func (stream, "%s", arm_conditional[value]);
+			    break;
+
+			  case 'C':
+			    value ^= 1;
+			    func (stream, "%s", arm_conditional[value]);
+			    break;
+
 			  case 'S':
 			    if (value == 13 || value == 15)
 			      is_unpredictable = TRUE;