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| author | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2013-05-23 15:48:47 +0000 |
|---|---|---|
| committer | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2013-05-23 15:48:47 +0000 |
| commit | 6cf1d90c239bf3da9ac8b3cea667cca9c9e7e924 (patch) | |
| tree | 6e5e9aa1b5426a98bbfef59b95c80ef2152c6c66 /opcodes | |
| parent | ce70887aa8d17bd4acf188f4ebade9cd2717acef (diff) | |
| download | gdb-6cf1d90c239bf3da9ac8b3cea667cca9c9e7e924.zip gdb-6cf1d90c239bf3da9ac8b3cea667cca9c9e7e924.tar.gz gdb-6cf1d90c239bf3da9ac8b3cea667cca9c9e7e924.tar.bz2 | |
2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
instruction format.
2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-zEC12.d: Adjust length operands for cdzt, cxzt,
czdt, and czxt.
* gas/s390/zarch-zEC12.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/s390-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 94cd05d..eb16b0a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU + instruction format. + 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 0ae5603..adfc5b4 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -388,8 +388,8 @@ const struct s390_operand s390_operands[] = #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ -#define INSTR_RSL_LRDFU 6, { F_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cdzt */ -#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cxzt */ +#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ +#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ |