Eliminate ia64 compiler warnings. Fix ia64 gas testsuite again.

	*  elfxx-ia64.c (get_dyn_sym_info): Cast %p argument to void *.
	* config/tc-ia64.h (ia64_init): Add prototype.
	* gas/ia64/dv-imply.d, gas/ia64/dv-mutex.d, gas/ia64/dv-safe.d,
	gas/ia64/dv-srlz.d, gas/ia64/opc-m.d: Update.
	* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
	argument.
	* ia64_gen.c (insert_deplist): Cast sizeof result to int.
	(print_dependency_table): Print NULL if semantics field not set.
	(insert_opcode_dependencies): Mark cmp parameter as unused.
	(print_main_table): Use fprintf_vma to print long long fields.
	(main): Mark argv paramter as unused.  Convert to old style definition.
	* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
	* ia64-asmtab.c: Regnerate.

5 files changed, 728 insertions, 709 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a2af556..b84bcfd 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2000-12-12  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
+	argument.
+	* ia64_gen.c (insert_deplist): Cast sizeof result to int.
+	(print_dependency_table): Print NULL if semantics field not set.
+	(insert_opcode_dependencies): Mark cmp parameter as unused.
+	(print_main_table): Use fprintf_vma to print long long fields.
+	(main): Mark argv paramter as unused.  Convert to old style definition.
+	* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
+	* ia64-asmtab.c: Regnerate.
+
 2000-12-09  Nick Clifton  <nickc@redhat.com>
 
 	* m32r-dis.c (print_insn): Prevent re-read of instruction from
diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c
index d08119d..e37e791 100644
--- a/opcodes/ia64-asmtab.c
+++ b/opcodes/ia64-asmtab.c
@@ -36,323 +36,323 @@ static const char *ia64_strings[] = {
 
 static const struct ia64_dependency
 dependencies[] = {
-  { "ALAT", 0, 0, 0, -1, },
-  { "AR[BSP]", 26, 0, 2, 17, },
-  { "AR[BSPSTORE]", 26, 0, 2, 18, },
-  { "AR[CCV]", 26, 0, 2, 32, },
-  { "AR[EC]", 26, 0, 2, 66, },
-  { "AR[FPSR].sf0.controls", 30, 0, 2, -1, },
-  { "AR[FPSR].sf1.controls", 30, 0, 2, -1, },
-  { "AR[FPSR].sf2.controls", 30, 0, 2, -1, },
-  { "AR[FPSR].sf3.controls", 30, 0, 2, -1, },
-  { "AR[FPSR].sf0.flags", 30, 0, 2, -1, },
-  { "AR[FPSR].sf1.flags", 30, 0, 2, -1, },
-  { "AR[FPSR].sf2.flags", 30, 0, 2, -1, },
-  { "AR[FPSR].sf3.flags", 30, 0, 2, -1, },
-  { "AR[FPSR].traps", 30, 0, 2, -1, },
-  { "AR[FPSR].rv", 30, 0, 2, -1, },
-  { "AR[ITC]", 26, 0, 2, 44, },
-  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, },
-  { "AR[LC]", 26, 0, 2, 65, },
-  { "AR[PFS]", 26, 0, 2, 64, },
-  { "AR[PFS]", 26, 0, 2, 64, },
-  { "AR[PFS]", 26, 0, 0, 64, },
-  { "AR[RNAT]", 26, 0, 2, 19, },
-  { "AR[RSC]", 26, 0, 2, 16, },
-  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, },
-  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, },
-  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 0, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 0, 0, -1, },
-  { "BR%, % in 0 - 7", 5, 0, 2, -1, },
-  { "CFM", 6, 0, 2, -1, },
-  { "CFM", 6, 0, 2, -1, },
-  { "CFM", 6, 0, 2, -1, },
-  { "CFM", 6, 0, 2, -1, },
-  { "CFM", 6, 0, 0, -1, },
-  { "CPUID#", 7, 0, 5, -1, },
-  { "CR[CMCV]", 27, 0, 3, 74, },
-  { "CR[DCR]", 27, 0, 3, 0, },
+  { "ALAT", 0, 0, 0, -1, NULL, },
+  { "AR[BSP]", 26, 0, 2, 17, NULL, },
+  { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
+  { "AR[CCV]", 26, 0, 2, 32, NULL, },
+  { "AR[EC]", 26, 0, 2, 66, NULL, },
+  { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
+  { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
+  { "AR[ITC]", 26, 0, 2, 44, NULL, },
+  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
+  { "AR[LC]", 26, 0, 2, 65, NULL, },
+  { "AR[PFS]", 26, 0, 2, 64, NULL, },
+  { "AR[PFS]", 26, 0, 2, 64, NULL, },
+  { "AR[PFS]", 26, 0, 0, 64, NULL, },
+  { "AR[RNAT]", 26, 0, 2, 19, NULL, },
+  { "AR[RSC]", 26, 0, 2, 16, NULL, },
+  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
+  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
+  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
+  { "CFM", 6, 0, 2, -1, NULL, },
+  { "CFM", 6, 0, 2, -1, NULL, },
+  { "CFM", 6, 0, 2, -1, NULL, },
+  { "CFM", 6, 0, 2, -1, NULL, },
+  { "CFM", 6, 0, 0, -1, NULL, },
+  { "CPUID#", 7, 0, 5, -1, NULL, },
+  { "CR[CMCV]", 27, 0, 3, 74, NULL, },
+  { "CR[DCR]", 27, 0, 3, 0, NULL, },
   { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", },
-  { "CR[GPTA]", 27, 0, 3, 9, },
-  { "CR[IFA]", 27, 0, 1, 20, },
-  { "CR[IFA]", 27, 0, 3, 20, },
-  { "CR[IFS]", 27, 0, 3, 23, },
-  { "CR[IFS]", 27, 0, 1, 23, },
-  { "CR[IFS]", 27, 0, 1, 23, },
-  { "CR[IHA]", 27, 0, 3, 25, },
-  { "CR[IIM]", 27, 0, 3, 24, },
-  { "CR[IIP]", 27, 0, 3, 19, },
-  { "CR[IIP]", 27, 0, 1, 19, },
-  { "CR[IIPA]", 27, 0, 3, 22, },
-  { "CR[IPSR]", 27, 0, 3, 16, },
-  { "CR[IPSR]", 27, 0, 1, 16, },
-  { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, },
-  { "CR[ISR]", 27, 0, 3, 17, },
-  { "CR[ITIR]", 27, 0, 3, 21, },
-  { "CR[ITIR]", 27, 0, 1, 21, },
-  { "CR[ITM]", 27, 0, 3, 1, },
-  { "CR[ITV]", 27, 0, 3, 72, },
-  { "CR[IVA]", 27, 0, 4, 2, },
+  { "CR[GPTA]", 27, 0, 3, 9, NULL, },
+  { "CR[IFA]", 27, 0, 1, 20, NULL, },
+  { "CR[IFA]", 27, 0, 3, 20, NULL, },
+  { "CR[IFS]", 27, 0, 3, 23, NULL, },
+  { "CR[IFS]", 27, 0, 1, 23, NULL, },
+  { "CR[IFS]", 27, 0, 1, 23, NULL, },
+  { "CR[IHA]", 27, 0, 3, 25, NULL, },
+  { "CR[IIM]", 27, 0, 3, 24, NULL, },
+  { "CR[IIP]", 27, 0, 3, 19, NULL, },
+  { "CR[IIP]", 27, 0, 1, 19, NULL, },
+  { "CR[IIPA]", 27, 0, 3, 22, NULL, },
+  { "CR[IPSR]", 27, 0, 3, 16, NULL, },
+  { "CR[IPSR]", 27, 0, 1, 16, NULL, },
+  { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },
+  { "CR[ISR]", 27, 0, 3, 17, NULL, },
+  { "CR[ITIR]", 27, 0, 3, 21, NULL, },
+  { "CR[ITIR]", 27, 0, 1, 21, NULL, },
+  { "CR[ITM]", 27, 0, 3, 1, NULL, },
+  { "CR[ITV]", 27, 0, 3, 72, NULL, },
+  { "CR[IVA]", 27, 0, 4, 2, NULL, },
   { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", },
   { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", },
-  { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, },
-  { "CR[PMV]", 27, 0, 3, 73, },
-  { "CR[PTA]", 27, 0, 3, 8, },
-  { "CR[TPR]", 27, 0, 3, 66, },
+  { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },
+  { "CR[PMV]", 27, 0, 3, 73, NULL, },
+  { "CR[PTA]", 27, 0, 3, 8, NULL, },
+  { "CR[TPR]", 27, 0, 3, 66, NULL, },
   { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", },
-  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, },
-  { "DBR#", 11, 0, 2, -1, },
-  { "DBR#", 11, 0, 3, -1, },
-  { "DTC", 0, 0, 3, -1, },
-  { "DTC", 0, 0, 2, -1, },
-  { "DTC", 0, 0, 0, -1, },
-  { "DTC", 0, 0, 2, -1, },
-  { "DTC_LIMIT*", 0, 0, 2, -1, },
-  { "DTR", 0, 0, 3, -1, },
-  { "DTR", 0, 0, 2, -1, },
-  { "DTR", 0, 0, 3, -1, },
-  { "DTR", 0, 0, 0, -1, },
-  { "DTR", 0, 0, 2, -1, },
-  { "FR%, % in 0 - 1", 12, 0, 0, -1, },
-  { "FR%, % in 2 - 127", 13, 0, 2, -1, },
-  { "FR%, % in 2 - 127", 13, 0, 0, -1, },
-  { "GR0", 14, 0, 0, -1, },
-  { "GR%, % in 1 - 127", 15, 0, 0, -1, },
-  { "GR%, % in 1 - 127", 15, 0, 2, -1, },
-  { "IBR#", 16, 0, 2, -1, },
-  { "InService*", 17, 0, 3, -1, },
-  { "InService*", 17, 0, 2, -1, },
-  { "InService*", 17, 0, 2, -1, },
-  { "IP", 0, 0, 0, -1, },
-  { "ITC", 0, 0, 4, -1, },
-  { "ITC", 0, 0, 2, -1, },
-  { "ITC", 0, 0, 0, -1, },
-  { "ITC", 0, 0, 4, -1, },
-  { "ITC", 0, 0, 2, -1, },
-  { "ITC_LIMIT*", 0, 0, 2, -1, },
-  { "ITR", 0, 0, 2, -1, },
-  { "ITR", 0, 0, 4, -1, },
-  { "ITR", 0, 0, 2, -1, },
-  { "ITR", 0, 0, 0, -1, },
-  { "ITR", 0, 0, 4, -1, },
-  { "memory", 0, 0, 0, -1, },
-  { "MSR#", 18, 0, 5, -1, },
-  { "PKR#", 19, 0, 3, -1, },
-  { "PKR#", 19, 0, 0, -1, },
-  { "PKR#", 19, 0, 2, -1, },
-  { "PKR#", 19, 0, 2, -1, },
-  { "PMC#", 20, 0, 2, -1, },
+  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },
+  { "DBR#", 11, 0, 2, -1, NULL, },
+  { "DBR#", 11, 0, 3, -1, NULL, },
+  { "DTC", 0, 0, 3, -1, NULL, },
+  { "DTC", 0, 0, 2, -1, NULL, },
+  { "DTC", 0, 0, 0, -1, NULL, },
+  { "DTC", 0, 0, 2, -1, NULL, },
+  { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },
+  { "DTR", 0, 0, 3, -1, NULL, },
+  { "DTR", 0, 0, 2, -1, NULL, },
+  { "DTR", 0, 0, 3, -1, NULL, },
+  { "DTR", 0, 0, 0, -1, NULL, },
+  { "DTR", 0, 0, 2, -1, NULL, },
+  { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },
+  { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },
+  { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },
+  { "GR0", 14, 0, 0, -1, NULL, },
+  { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },
+  { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },
+  { "IBR#", 16, 0, 2, -1, NULL, },
+  { "InService*", 17, 0, 3, -1, NULL, },
+  { "InService*", 17, 0, 2, -1, NULL, },
+  { "InService*", 17, 0, 2, -1, NULL, },
+  { "IP", 0, 0, 0, -1, NULL, },
+  { "ITC", 0, 0, 4, -1, NULL, },
+  { "ITC", 0, 0, 2, -1, NULL, },
+  { "ITC", 0, 0, 0, -1, NULL, },
+  { "ITC", 0, 0, 4, -1, NULL, },
+  { "ITC", 0, 0, 2, -1, NULL, },
+  { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },
+  { "ITR", 0, 0, 2, -1, NULL, },
+  { "ITR", 0, 0, 4, -1, NULL, },
+  { "ITR", 0, 0, 2, -1, NULL, },
+  { "ITR", 0, 0, 0, -1, NULL, },
+  { "ITR", 0, 0, 4, -1, NULL, },
+  { "memory", 0, 0, 0, -1, NULL, },
+  { "MSR#", 18, 0, 5, -1, NULL, },
+  { "PKR#", 19, 0, 3, -1, NULL, },
+  { "PKR#", 19, 0, 0, -1, NULL, },
+  { "PKR#", 19, 0, 2, -1, NULL, },
+  { "PKR#", 19, 0, 2, -1, NULL, },
+  { "PMC#", 20, 0, 2, -1, NULL, },
   { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", },
-  { "PMD#", 21, 0, 2, -1, },
-  { "PR0", 0, 0, 0, -1, },
-  { "PR%, % in 1 - 15", 22, 0, 2, -1, },
-  { "PR%, % in 1 - 15", 22, 0, 2, -1, },
-  { "PR%, % in 1 - 15", 22, 0, 0, -1, },
-  { "PR%, % in 16 - 62", 23, 0, 2, -1, },
-  { "PR%, % in 16 - 62", 23, 0, 2, -1, },
-  { "PR%, % in 16 - 62", 23, 0, 0, -1, },
-  { "PR63", 24, 0, 2, -1, },
-  { "PR63", 24, 0, 2, -1, },
-  { "PR63", 24, 0, 0, -1, },
-  { "PSR.ac", 28, 0, 1, 3, },
-  { "PSR.ac", 28, 0, 3, 3, },
-  { "PSR.ac", 28, 0, 2, 3, },
-  { "PSR.be", 28, 0, 1, 1, },
-  { "PSR.be", 28, 0, 3, 1, },
-  { "PSR.be", 28, 0, 2, 1, },
-  { "PSR.bn", 28, 0, 2, 44, },
-  { "PSR.cpl", 28, 0, 1, 32, },
-  { "PSR.da", 28, 0, 3, 38, },
-  { "PSR.db", 28, 0, 3, 24, },
-  { "PSR.db", 28, 0, 2, 24, },
-  { "PSR.db", 28, 0, 3, 24, },
-  { "PSR.dd", 28, 0, 3, 39, },
-  { "PSR.dfh", 28, 0, 3, 19, },
-  { "PSR.dfh", 28, 0, 2, 19, },
-  { "PSR.dfl", 28, 0, 3, 18, },
-  { "PSR.dfl", 28, 0, 2, 18, },
-  { "PSR.di", 28, 0, 3, 22, },
-  { "PSR.di", 28, 0, 2, 22, },
-  { "PSR.dt", 28, 0, 3, 17, },
-  { "PSR.dt", 28, 0, 2, 17, },
-  { "PSR.ed", 28, 0, 3, 43, },
-  { "PSR.i", 28, 0, 2, 14, },
-  { "PSR.i", 28, 0, 3, 14, },
-  { "PSR.ia", 28, 0, 0, 14, },
-  { "PSR.ic", 28, 0, 2, 13, },
-  { "PSR.ic", 28, 0, 3, 13, },
-  { "PSR.id", 28, 0, 0, 14, },
-  { "PSR.is", 28, 0, 0, 14, },
-  { "PSR.it", 28, 0, 3, 14, },
-  { "PSR.lp", 28, 0, 2, 25, },
-  { "PSR.lp", 28, 0, 3, 25, },
-  { "PSR.lp", 28, 0, 3, 25, },
-  { "PSR.mc", 28, 0, 0, 35, },
-  { "PSR.mfh", 28, 0, 2, 5, },
-  { "PSR.mfl", 28, 0, 2, 4, },
-  { "PSR.pk", 28, 0, 3, 15, },
-  { "PSR.pk", 28, 0, 2, 15, },
-  { "PSR.pp", 28, 0, 2, 21, },
-  { "PSR.ri", 28, 0, 0, 41, },
-  { "PSR.rt", 28, 0, 2, 27, },
-  { "PSR.rt", 28, 0, 3, 27, },
-  { "PSR.rt", 28, 0, 3, 27, },
-  { "PSR.si", 28, 0, 2, 23, },
-  { "PSR.si", 28, 0, 3, 23, },
-  { "PSR.sp", 28, 0, 2, 20, },
-  { "PSR.sp", 28, 0, 3, 20, },
-  { "PSR.ss", 28, 0, 3, 40, },
-  { "PSR.tb", 28, 0, 3, 26, },
-  { "PSR.tb", 28, 0, 2, 26, },
-  { "PSR.up", 28, 0, 2, 2, },
-  { "RR#", 25, 0, 3, -1, },
-  { "RR#", 25, 0, 2, -1, },
-  { "RSE", 29, 0, 2, -1, },
-  { "ALAT", 0, 1, 0, -1, },
-  { "AR[BSP]", 26, 1, 2, 17, },
-  { "AR[BSPSTORE]", 26, 1, 2, 18, },
-  { "AR[CCV]", 26, 1, 2, 32, },
-  { "AR[EC]", 26, 1, 2, 66, },
-  { "AR[FPSR].sf0.controls", 30, 1, 2, -1, },
-  { "AR[FPSR].sf1.controls", 30, 1, 2, -1, },
-  { "AR[FPSR].sf2.controls", 30, 1, 2, -1, },
-  { "AR[FPSR].sf3.controls", 30, 1, 2, -1, },
-  { "AR[FPSR].sf0.flags", 30, 1, 0, -1, },
-  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf1.flags", 30, 1, 0, -1, },
-  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf2.flags", 30, 1, 0, -1, },
-  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf3.flags", 30, 1, 0, -1, },
-  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, },
-  { "AR[FPSR].rv", 30, 1, 2, -1, },
-  { "AR[FPSR].traps", 30, 1, 2, -1, },
-  { "AR[ITC]", 26, 1, 2, 44, },
-  { "AR[K%], % in 0 - 7", 1, 1, 2, -1, },
-  { "AR[LC]", 26, 1, 2, 65, },
-  { "AR[PFS]", 26, 1, 0, 64, },
-  { "AR[PFS]", 26, 1, 2, 64, },
-  { "AR[PFS]", 26, 1, 2, 64, },
-  { "AR[RNAT]", 26, 1, 2, 19, },
-  { "AR[RSC]", 26, 1, 2, 16, },
-  { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, },
-  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, },
-  { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
-  { "BR%, % in 0 - 7", 5, 1, 0, -1, },
-  { "CFM", 6, 1, 2, -1, },
-  { "CPUID#", 7, 1, 0, -1, },
-  { "CR[CMCV]", 27, 1, 2, 74, },
-  { "CR[DCR]", 27, 1, 2, 0, },
+  { "PMD#", 21, 0, 2, -1, NULL, },
+  { "PR0", 0, 0, 0, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },
+  { "PR63", 24, 0, 2, -1, NULL, },
+  { "PR63", 24, 0, 2, -1, NULL, },
+  { "PR63", 24, 0, 0, -1, NULL, },
+  { "PSR.ac", 28, 0, 1, 3, NULL, },
+  { "PSR.ac", 28, 0, 3, 3, NULL, },
+  { "PSR.ac", 28, 0, 2, 3, NULL, },
+  { "PSR.be", 28, 0, 1, 1, NULL, },
+  { "PSR.be", 28, 0, 3, 1, NULL, },
+  { "PSR.be", 28, 0, 2, 1, NULL, },
+  { "PSR.bn", 28, 0, 2, 44, NULL, },
+  { "PSR.cpl", 28, 0, 1, 32, NULL, },
+  { "PSR.da", 28, 0, 3, 38, NULL, },
+  { "PSR.db", 28, 0, 3, 24, NULL, },
+  { "PSR.db", 28, 0, 2, 24, NULL, },
+  { "PSR.db", 28, 0, 3, 24, NULL, },
+  { "PSR.dd", 28, 0, 3, 39, NULL, },
+  { "PSR.dfh", 28, 0, 3, 19, NULL, },
+  { "PSR.dfh", 28, 0, 2, 19, NULL, },
+  { "PSR.dfl", 28, 0, 3, 18, NULL, },
+  { "PSR.dfl", 28, 0, 2, 18, NULL, },
+  { "PSR.di", 28, 0, 3, 22, NULL, },
+  { "PSR.di", 28, 0, 2, 22, NULL, },
+  { "PSR.dt", 28, 0, 3, 17, NULL, },
+  { "PSR.dt", 28, 0, 2, 17, NULL, },
+  { "PSR.ed", 28, 0, 3, 43, NULL, },
+  { "PSR.i", 28, 0, 2, 14, NULL, },
+  { "PSR.i", 28, 0, 3, 14, NULL, },
+  { "PSR.ia", 28, 0, 0, 14, NULL, },
+  { "PSR.ic", 28, 0, 2, 13, NULL, },
+  { "PSR.ic", 28, 0, 3, 13, NULL, },
+  { "PSR.id", 28, 0, 0, 14, NULL, },
+  { "PSR.is", 28, 0, 0, 14, NULL, },
+  { "PSR.it", 28, 0, 3, 14, NULL, },
+  { "PSR.lp", 28, 0, 2, 25, NULL, },
+  { "PSR.lp", 28, 0, 3, 25, NULL, },
+  { "PSR.lp", 28, 0, 3, 25, NULL, },
+  { "PSR.mc", 28, 0, 0, 35, NULL, },
+  { "PSR.mfh", 28, 0, 2, 5, NULL, },
+  { "PSR.mfl", 28, 0, 2, 4, NULL, },
+  { "PSR.pk", 28, 0, 3, 15, NULL, },
+  { "PSR.pk", 28, 0, 2, 15, NULL, },
+  { "PSR.pp", 28, 0, 2, 21, NULL, },
+  { "PSR.ri", 28, 0, 0, 41, NULL, },
+  { "PSR.rt", 28, 0, 2, 27, NULL, },
+  { "PSR.rt", 28, 0, 3, 27, NULL, },
+  { "PSR.rt", 28, 0, 3, 27, NULL, },
+  { "PSR.si", 28, 0, 2, 23, NULL, },
+  { "PSR.si", 28, 0, 3, 23, NULL, },
+  { "PSR.sp", 28, 0, 2, 20, NULL, },
+  { "PSR.sp", 28, 0, 3, 20, NULL, },
+  { "PSR.ss", 28, 0, 3, 40, NULL, },
+  { "PSR.tb", 28, 0, 3, 26, NULL, },
+  { "PSR.tb", 28, 0, 2, 26, NULL, },
+  { "PSR.up", 28, 0, 2, 2, NULL, },
+  { "RR#", 25, 0, 3, -1, NULL, },
+  { "RR#", 25, 0, 2, -1, NULL, },
+  { "RSE", 29, 0, 2, -1, NULL, },
+  { "ALAT", 0, 1, 0, -1, NULL, },
+  { "AR[BSP]", 26, 1, 2, 17, NULL, },
+  { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },
+  { "AR[CCV]", 26, 1, 2, 32, NULL, },
+  { "AR[EC]", 26, 1, 2, 66, NULL, },
+  { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },
+  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },
+  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },
+  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },
+  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },
+  { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },
+  { "AR[ITC]", 26, 1, 2, 44, NULL, },
+  { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },
+  { "AR[LC]", 26, 1, 2, 65, NULL, },
+  { "AR[PFS]", 26, 1, 0, 64, NULL, },
+  { "AR[PFS]", 26, 1, 2, 64, NULL, },
+  { "AR[PFS]", 26, 1, 2, 64, NULL, },
+  { "AR[RNAT]", 26, 1, 2, 19, NULL, },
+  { "AR[RSC]", 26, 1, 2, 16, NULL, },
+  { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },
+  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },
+  { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
+  { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, },
+  { "CFM", 6, 1, 2, -1, NULL, },
+  { "CPUID#", 7, 1, 0, -1, NULL, },
+  { "CR[CMCV]", 27, 1, 2, 74, NULL, },
+  { "CR[DCR]", 27, 1, 2, 0, NULL, },
   { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", },
-  { "CR[GPTA]", 27, 1, 2, 9, },
-  { "CR[IFA]", 27, 1, 2, 20, },
-  { "CR[IFS]", 27, 1, 2, 23, },
-  { "CR[IHA]", 27, 1, 2, 25, },
-  { "CR[IIM]", 27, 1, 2, 24, },
-  { "CR[IIP]", 27, 1, 2, 19, },
-  { "CR[IIPA]", 27, 1, 2, 22, },
-  { "CR[IPSR]", 27, 1, 2, 16, },
-  { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, },
-  { "CR[ISR]", 27, 1, 2, 17, },
-  { "CR[ITIR]", 27, 1, 2, 21, },
-  { "CR[ITM]", 27, 1, 2, 1, },
-  { "CR[ITV]", 27, 1, 2, 72, },
-  { "CR[IVA]", 27, 1, 2, 2, },
+  { "CR[GPTA]", 27, 1, 2, 9, NULL, },
+  { "CR[IFA]", 27, 1, 2, 20, NULL, },
+  { "CR[IFS]", 27, 1, 2, 23, NULL, },
+  { "CR[IHA]", 27, 1, 2, 25, NULL, },
+  { "CR[IIM]", 27, 1, 2, 24, NULL, },
+  { "CR[IIP]", 27, 1, 2, 19, NULL, },
+  { "CR[IIPA]", 27, 1, 2, 22, NULL, },
+  { "CR[IPSR]", 27, 1, 2, 16, NULL, },
+  { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, },
+  { "CR[ISR]", 27, 1, 2, 17, NULL, },
+  { "CR[ITIR]", 27, 1, 2, 21, NULL, },
+  { "CR[ITM]", 27, 1, 2, 1, NULL, },
+  { "CR[ITV]", 27, 1, 2, 72, NULL, },
+  { "CR[IVA]", 27, 1, 2, 2, NULL, },
   { "CR[IVR]", 27, 1, 7, 65, "SC", },
   { "CR[LID]", 27, 1, 7, 64, "SC", },
-  { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, },
-  { "CR[PMV]", 27, 1, 2, 73, },
-  { "CR[PTA]", 27, 1, 2, 8, },
-  { "CR[TPR]", 27, 1, 2, 66, },
-  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, },
-  { "DBR#", 11, 1, 2, -1, },
-  { "DTC", 0, 1, 0, -1, },
-  { "DTC", 0, 1, 2, -1, },
-  { "DTC", 0, 1, 2, -1, },
-  { "DTC_LIMIT*", 0, 1, 2, -1, },
-  { "DTR", 0, 1, 2, -1, },
-  { "DTR", 0, 1, 2, -1, },
-  { "DTR", 0, 1, 2, -1, },
-  { "DTR", 0, 1, 0, -1, },
-  { "FR%, % in 0 - 1", 12, 1, 0, -1, },
-  { "FR%, % in 2 - 127", 13, 1, 2, -1, },
-  { "GR0", 14, 1, 0, -1, },
-  { "GR%, % in 1 - 127", 15, 1, 2, -1, },
-  { "IBR#", 16, 1, 2, -1, },
+  { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, },
+  { "CR[PMV]", 27, 1, 2, 73, NULL, },
+  { "CR[PTA]", 27, 1, 2, 8, NULL, },
+  { "CR[TPR]", 27, 1, 2, 66, NULL, },
+  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, },
+  { "DBR#", 11, 1, 2, -1, NULL, },
+  { "DTC", 0, 1, 0, -1, NULL, },
+  { "DTC", 0, 1, 2, -1, NULL, },
+  { "DTC", 0, 1, 2, -1, NULL, },
+  { "DTC_LIMIT*", 0, 1, 2, -1, NULL, },
+  { "DTR", 0, 1, 2, -1, NULL, },
+  { "DTR", 0, 1, 2, -1, NULL, },
+  { "DTR", 0, 1, 2, -1, NULL, },
+  { "DTR", 0, 1, 0, -1, NULL, },
+  { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, },
+  { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, },
+  { "GR0", 14, 1, 0, -1, NULL, },
+  { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, },
+  { "IBR#", 16, 1, 2, -1, NULL, },
   { "InService*", 17, 1, 7, -1, "SC", },
-  { "IP", 0, 1, 0, -1, },
-  { "ITC", 0, 1, 0, -1, },
-  { "ITC", 0, 1, 2, -1, },
-  { "ITC", 0, 1, 2, -1, },
-  { "ITR", 0, 1, 2, -1, },
-  { "ITR", 0, 1, 2, -1, },
-  { "ITR", 0, 1, 0, -1, },
-  { "memory", 0, 1, 0, -1, },
+  { "IP", 0, 1, 0, -1, NULL, },
+  { "ITC", 0, 1, 0, -1, NULL, },
+  { "ITC", 0, 1, 2, -1, NULL, },
+  { "ITC", 0, 1, 2, -1, NULL, },
+  { "ITR", 0, 1, 2, -1, NULL, },
+  { "ITR", 0, 1, 2, -1, NULL, },
+  { "ITR", 0, 1, 0, -1, NULL, },
+  { "memory", 0, 1, 0, -1, NULL, },
   { "MSR#", 18, 1, 7, -1, "SC", },
-  { "PKR#", 19, 1, 0, -1, },
-  { "PKR#", 19, 1, 0, -1, },
-  { "PKR#", 19, 1, 2, -1, },
-  { "PMC#", 20, 1, 2, -1, },
-  { "PMD#", 21, 1, 2, -1, },
-  { "PR0", 0, 1, 0, -1, },
-  { "PR%, % in 1 - 15", 22, 1, 0, -1, },
-  { "PR%, % in 1 - 15", 22, 1, 0, -1, },
-  { "PR%, % in 1 - 15", 22, 1, 2, -1, },
-  { "PR%, % in 1 - 15", 22, 1, 2, -1, },
-  { "PR%, % in 16 - 62", 23, 1, 0, -1, },
-  { "PR%, % in 16 - 62", 23, 1, 0, -1, },
-  { "PR%, % in 16 - 62", 23, 1, 2, -1, },
-  { "PR%, % in 16 - 62", 23, 1, 2, -1, },
-  { "PR63", 24, 1, 0, -1, },
-  { "PR63", 24, 1, 0, -1, },
-  { "PR63", 24, 1, 2, -1, },
-  { "PR63", 24, 1, 2, -1, },
-  { "PSR.ac", 28, 1, 2, 3, },
-  { "PSR.be", 28, 1, 2, 1, },
-  { "PSR.bn", 28, 1, 2, 44, },
-  { "PSR.cpl", 28, 1, 2, 32, },
-  { "PSR.da", 28, 1, 2, 38, },
-  { "PSR.db", 28, 1, 2, 24, },
-  { "PSR.dd", 28, 1, 2, 39, },
-  { "PSR.dfh", 28, 1, 2, 19, },
-  { "PSR.dfl", 28, 1, 2, 18, },
-  { "PSR.di", 28, 1, 2, 22, },
-  { "PSR.dt", 28, 1, 2, 17, },
-  { "PSR.ed", 28, 1, 2, 43, },
-  { "PSR.i", 28, 1, 2, 14, },
-  { "PSR.ia", 28, 1, 2, 14, },
-  { "PSR.ic", 28, 1, 2, 13, },
-  { "PSR.id", 28, 1, 2, 14, },
-  { "PSR.is", 28, 1, 2, 14, },
-  { "PSR.it", 28, 1, 2, 14, },
-  { "PSR.lp", 28, 1, 2, 25, },
-  { "PSR.mc", 28, 1, 2, 35, },
-  { "PSR.mfh", 28, 1, 0, 5, },
-  { "PSR.mfh", 28, 1, 2, 5, },
-  { "PSR.mfh", 28, 1, 2, 5, },
-  { "PSR.mfl", 28, 1, 0, 4, },
-  { "PSR.mfl", 28, 1, 2, 4, },
-  { "PSR.mfl", 28, 1, 2, 4, },
-  { "PSR.pk", 28, 1, 2, 15, },
-  { "PSR.pp", 28, 1, 2, 21, },
-  { "PSR.ri", 28, 1, 2, 41, },
-  { "PSR.rt", 28, 1, 2, 27, },
-  { "PSR.si", 28, 1, 2, 23, },
-  { "PSR.sp", 28, 1, 2, 20, },
-  { "PSR.ss", 28, 1, 2, 40, },
-  { "PSR.tb", 28, 1, 2, 26, },
-  { "PSR.up", 28, 1, 2, 2, },
-  { "RR#", 25, 1, 2, -1, },
-  { "RSE", 29, 1, 2, -1, },
-  { "PR63", 24, 2, 6, -1, },
+  { "PKR#", 19, 1, 0, -1, NULL, },
+  { "PKR#", 19, 1, 0, -1, NULL, },
+  { "PKR#", 19, 1, 2, -1, NULL, },
+  { "PMC#", 20, 1, 2, -1, NULL, },
+  { "PMD#", 21, 1, 2, -1, NULL, },
+  { "PR0", 0, 1, 0, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
+  { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
+  { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
+  { "PR63", 24, 1, 0, -1, NULL, },
+  { "PR63", 24, 1, 0, -1, NULL, },
+  { "PR63", 24, 1, 2, -1, NULL, },
+  { "PR63", 24, 1, 2, -1, NULL, },
+  { "PSR.ac", 28, 1, 2, 3, NULL, },
+  { "PSR.be", 28, 1, 2, 1, NULL, },
+  { "PSR.bn", 28, 1, 2, 44, NULL, },
+  { "PSR.cpl", 28, 1, 2, 32, NULL, },
+  { "PSR.da", 28, 1, 2, 38, NULL, },
+  { "PSR.db", 28, 1, 2, 24, NULL, },
+  { "PSR.dd", 28, 1, 2, 39, NULL, },
+  { "PSR.dfh", 28, 1, 2, 19, NULL, },
+  { "PSR.dfl", 28, 1, 2, 18, NULL, },
+  { "PSR.di", 28, 1, 2, 22, NULL, },
+  { "PSR.dt", 28, 1, 2, 17, NULL, },
+  { "PSR.ed", 28, 1, 2, 43, NULL, },
+  { "PSR.i", 28, 1, 2, 14, NULL, },
+  { "PSR.ia", 28, 1, 2, 14, NULL, },
+  { "PSR.ic", 28, 1, 2, 13, NULL, },
+  { "PSR.id", 28, 1, 2, 14, NULL, },
+  { "PSR.is", 28, 1, 2, 14, NULL, },
+  { "PSR.it", 28, 1, 2, 14, NULL, },
+  { "PSR.lp", 28, 1, 2, 25, NULL, },
+  { "PSR.mc", 28, 1, 2, 35, NULL, },
+  { "PSR.mfh", 28, 1, 0, 5, NULL, },
+  { "PSR.mfh", 28, 1, 2, 5, NULL, },
+  { "PSR.mfh", 28, 1, 2, 5, NULL, },
+  { "PSR.mfl", 28, 1, 0, 4, NULL, },
+  { "PSR.mfl", 28, 1, 2, 4, NULL, },
+  { "PSR.mfl", 28, 1, 2, 4, NULL, },
+  { "PSR.pk", 28, 1, 2, 15, NULL, },
+  { "PSR.pp", 28, 1, 2, 21, NULL, },
+  { "PSR.ri", 28, 1, 2, 41, NULL, },
+  { "PSR.rt", 28, 1, 2, 27, NULL, },
+  { "PSR.si", 28, 1, 2, 23, NULL, },
+  { "PSR.sp", 28, 1, 2, 20, NULL, },
+  { "PSR.ss", 28, 1, 2, 40, NULL, },
+  { "PSR.tb", 28, 1, 2, 26, NULL, },
+  { "PSR.up", 28, 1, 2, 2, NULL, },
+  { "RR#", 25, 1, 2, -1, NULL, },
+  { "RSE", 29, 1, 2, -1, NULL, },
+  { "PR63", 24, 2, 6, -1, NULL, },
 };
 
 static const short dep0[] = {
@@ -4094,398 +4094,398 @@ completer_table[] = {
 
 static const struct ia64_main_table
 main_table[] = {
-  { 5, 1, 1, 0x10000000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
-  { 5, 1, 1, 0x10008000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, },
-  { 5, 7, 1, 0x0ull, 0x0ull, { 23, 65, 25, 0, 0 }, 0x0, 2, },
-  { 6, 1, 1, 0x12000000000ull, 0x1e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 3, },
-  { 7, 1, 1, 0x10040000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 4, },
-  { 7, 1, 1, 0x10c00000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 5, },
-  { 8, 1, 1, 0x10800000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, },
-  { 9, 3, 1, 0x2c00000000ull, 0x1ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 7, },
-  { 10, 1, 1, 0x10060000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 8, },
-  { 10, 1, 1, 0x10160000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 9, },
-  { 11, 1, 1, 0x10068000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 10, },
-  { 11, 1, 1, 0x10168000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 11, },
-  { 14, 4, 0, 0x100000000ull, 0x1eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 781, },
-  { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 647, },
-  { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 648, },
-  { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1770, },
-  { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1771, },
-  { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 404, },
-  { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 405, },
-  { 14, 4, 0, 0x8000000000ull, 0x1ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 802, },
-  { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 649, },
-  { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 650, },
-  { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2406, },
-  { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2407, },
-  { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 412, },
-  { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 413, },
-  { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 410, },
-  { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 411, },
-  { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 406, },
-  { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 407, },
-  { 15, 4, 0, 0x0ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 360, },
-  { 15, 5, 0, 0x0ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 773, },
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+  { 248, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 200, },
+  { 249, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 201, },
+  { 250, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 918, },
+  { 251, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 202, },
+  { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 2416, },
+  { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 1675, },
+  { 253, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 203, },
+  { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 2418, },
+  { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 1677, },
+  { 255, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 204, },
+  { 257, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 205, },
+  { 261, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 901, },
+  { 262, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 902, },
+  { 263, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 903, },
+  { 271, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 206, },
+  { 272, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 207, },
+  { 273, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 208, },
+  { 274, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 209, },
+  { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 947, },
+  { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 987, },
+  { 277, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 948, },
+  { 278, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 210, },
+  { 278, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 211, },
+  { 281, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 212, },
+  { 282, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 213, },
+  { 283, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 214, },
 };
 
 static const char dis_table[] = {
diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c
index c776abd..5e46796 100644
--- a/opcodes/ia64-dis.c
+++ b/opcodes/ia64-dis.c
@@ -261,7 +261,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
     (*info->fprintf_func) (info->stream, ";;");
 
  done:
-  ia64_free_opcode (idesc);
+  ia64_free_opcode ((struct ia64_opcode *)idesc);
  failed:
   if (slotnum == 2)
     retval += 16 - 3*slot_multiplier;
diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c
index f0451ce..e5e4e93 100644
--- a/opcodes/ia64-gen.c
+++ b/opcodes/ia64-gen.c
@@ -281,14 +281,14 @@ insert_deplist(int count, unsigned short *deps)
   for (i=0;i < count;i++)
     set[deps[i]] = 1;
   count = 0;
-  for (i=0;i < sizeof(set);i++)
+  for (i=0;i < (int)sizeof(set);i++)
     if (set[i])
       ++count;
 
   list = tmalloc(struct deplist);
   list->len = count;
   list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count);
-  for (i=0, count=0;i < sizeof(set);i++)
+  for (i=0, count=0;i < (int)sizeof(set);i++)
     {
       if (set[i])
         {
@@ -1459,6 +1459,8 @@ print_dependency_table ()
               (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex);
       if (rdeps[i]->semantics == IA64_DVS_OTHER)
         printf ("\"%s\", ", rdeps[i]->extra);
+      else
+	printf ("NULL, ");
       printf("},\n");
     }
   printf ("};\n\n");
@@ -2395,7 +2397,7 @@ collapse_redundant_completers ()
 int
 insert_opcode_dependencies (opc, cmp)
      struct ia64_opcode *opc;
-     struct completer_entry *cmp;
+     struct completer_entry *cmp ATTRIBUTE_UNUSED;
 {
   /* note all resources which point to this opcode.  rfi has the most chks
      (79) and cmpxchng has the most regs (54) so 100 here should be enough */
@@ -2701,12 +2703,14 @@ print_main_table ()
   printf ("static const struct ia64_main_table\nmain_table[] = {\n");
   while (ptr != NULL)
     {
-      printf ("  { %d, %d, %d, 0x%llxull, 0x%llxull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n",
+      printf ("  { %d, %d, %d, 0x",
 	      ptr->name->num,
 	      ptr->opcode->type,
-	      ptr->opcode->num_outputs,
-	      ptr->opcode->opcode,
-	      ptr->opcode->mask,
+	      ptr->opcode->num_outputs);
+      fprintf_vma (stdout, ptr->opcode->opcode);
+      printf ("ull, 0x");
+      fprintf_vma (stdout, ptr->opcode->mask);
+      printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n",
 	      ptr->opcode->operands[0],
 	      ptr->opcode->operands[1],
 	      ptr->opcode->operands[2],
@@ -2735,7 +2739,9 @@ shrink (table)
 }
 
 int
-main (int argc, char **argv)
+main (argc, argv)
+     int argc;
+     char **argv ATTRIBUTE_UNUSED;
 {
   if (argc > 1)
     {
diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c
index c054b3d..c2ddc87 100644
--- a/opcodes/ia64-opc.c
+++ b/opcodes/ia64-opc.c
@@ -740,7 +740,8 @@ ia64_find_dependency (index)
 {
   index = DEP(index);
 
-  if (index < 0 || index >= sizeof(dependencies) / sizeof(dependencies[0]))
+  if (index < 0
+      || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0])))
     return NULL;
 
   return &dependencies[index];