MIPS: Add CRC ASE support

Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 143-148

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 165-170

ChangeLog:

bfd/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elfxx-mips.c (print_mips_ases): Add CRC.

binutils/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* readelf.c (print_mips_ases): Add CRC.

gas/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mcrc and -mno-crc.
	(mips_ases): Define availability for CRC and CRC64.
	(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
	* doc/as.texinfo: Document -mcrc, -mno-crc.
	* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
	.set no-crc.
	* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
	ASE.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ase-errors-1.s: Likewise.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/crc.d: New test.
	* testsuite/gas/mips/crc64.d: New test.
	* testsuite/gas/mips/crc-err.d: New test.
	* testsuite/gas/mips/crc64-err.d: New test.
	* testsuite/gas/mips/crc-err.l: New test stderr output.
	* testsuite/gas/mips/crc64-err.l: New test stderr output.
	* testsuite/gas/mips/crc.s: New test source.
	* testsuite/gas/mips/crc64.s: New test source.
	* testsuite/gas/mips/crc-err.s: New test source.
	* testsuite/gas/mips/crc64-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elf/mips.h (AFL_ASE_CRC): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
	* opcode/mips.h (ASE_CRC): New macro.
	* opcode/mips.h (ASE_CRC64): Likewise.

opcodes/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
	* mips-opc.c (CRC, CRC64): New macros.
	(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
	crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
	crc32cd for CRC64.

3 files changed, 26 insertions, 2 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3a9720d..666238d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
+	    Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+	* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
+	* mips-opc.c (CRC, CRC64): New macros.
+	(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
+	crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
+	crc32cd for CRC64.
+
 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 
 	PR 20319
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 984fcbb..95a1937 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips32r6",	1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
     ISA_MIPS32R6,
     (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
-     | ASE_DSPR2 | ASE_DSPR3),
+     | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -602,7 +602,8 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips64r6",	1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
     ISA_MIPS64R6,
     (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
-     | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
+     | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
+     | ASE_CRC64),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b0c6195..d172801 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -404,6 +404,10 @@ decode_mips_operand (const char *p)
 #define XPA     ASE_XPA
 #define XPAVZ	ASE_XPA_VIRT
 
+/* Cyclic redundancy check instruction (CRC) support.  */
+#define CRC	ASE_CRC
+#define CRC64	ASE_CRC64
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -3347,6 +3351,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"aluipc",		"s,u",		0xec1f0000, 0xfc1f0000, WR_1,			RD_pc,		I37,		0,	0 },
 
+/* MIPS cyclic redundancy check (CRC) ASE.  */
+{"crc32b",		"t,s,-d",	0x7c00000f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32h",		"t,s,-d",	0x7c00004f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32w",		"t,s,-d",	0x7c00008f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32d",		"t,s,-d",	0x7c0000cf, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC64,	0 },
+{"crc32cb",		"t,s,-d",	0x7c00010f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32ch",		"t,s,-d",	0x7c00014f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32cw",		"t,s,-d",	0x7c00018f, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC,	0 },
+{"crc32cd",		"t,s,-d",	0x7c0001cf, 0xfc00ffff, MOD_1|RD_2,		0,		0,		CRC64,	0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the