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| author | Tamar Christina <tamar.christina@arm.com> | 2018-06-22 12:27:53 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-06-22 12:32:19 +0100 |
| commit | 514cd3a0f589fa48ca7bc9504c36436c0cbefcb2 (patch) | |
| tree | 560f31954190dcc24cfcaadb07dfd9d90e070883 /opcodes | |
| parent | bfd60e344c8001910825a358ad674003738ebb6b (diff) | |
| download | gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.zip gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.tar.gz gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.tar.bz2 | |
Correct negs aliasing on AArch64.
This patch fixes a disassembly issue with the aliases to subs with a shifted
register. The subs instruction with the zero register as destination is
supposed to alias to cmp and when the first input register is the zero register
the subs is supposed to be aliased to negs.
This means that a subs with destination and first input registers the zero
register is supposed to be a cmp.
This is done by raising the priority of the cmp alias.
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
gas/
* testsuite/gas/aarch64/addsub.s: Add negs to zero reg test.
* testsuite/gas/aarch64/addsub.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
4 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d455a38..2c2b975 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2018-06-19 Tamar Christina <tamar.christina@arm.com> + + * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + 2018-06-21 Maciej W. Rozycki <macro@mips.com> * mips-dis.c (print_mips_disassembler_options): Fix a typo in diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 01bc0e1..45b0085 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -66,8 +66,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case 22: /* sub */ value = 22; /* --> sub. */ break; - case 26: /* negs */ case 25: /* cmp */ + case 26: /* negs */ case 24: /* subs */ value = 24; /* --> subs. */ break; diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index cf0288f..5218297 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -19404,7 +19404,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) case 17: value = 18; break; /* subs --> cmp. */ case 20: value = 21; break; /* adds --> cmn. */ case 22: value = 23; break; /* sub --> neg. */ - case 24: value = 26; break; /* subs --> negs. */ + case 24: value = 25; break; /* subs --> cmp. */ case 150: value = 151; break; /* umov --> mov. */ case 152: value = 153; break; /* ins --> mov. */ case 154: value = 155; break; /* ins --> mov. */ @@ -19543,8 +19543,8 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case 18: value = 17; break; /* cmp --> subs. */ case 21: value = 20; break; /* cmn --> adds. */ case 23: value = 22; break; /* neg --> sub. */ - case 26: value = 25; break; /* negs --> cmp. */ - case 25: value = 24; break; /* cmp --> subs. */ + case 25: value = 26; break; /* cmp --> negs. */ + case 26: value = 24; break; /* negs --> subs. */ case 151: value = 150; break; /* mov --> umov. */ case 153: value = 152; break; /* mov --> ins. */ case 155: value = 154; break; /* mov --> ins. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1a35b3f..08eec60 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2266,7 +2266,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), - CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), + CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1), CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), /* AdvSIMD across lanes. */ SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |